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74LVCH16901DGGRE4 Fiches technique(PDF) 2 Page - Texas Instruments |
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74LVCH16901DGGRE4 Fiches technique(HTML) 2 Page - Texas Instruments |
2 / 13 page www.ti.com DESCRIPTION/ORDERING INFORMATION (CONTINUED) SN74LVCH16901 18-BIT UNIVERSAL BUS TRANSCEIVER WITH PARITY GENERATORS/CHECKERS SCES145C – OCTOBER 1998 – REVISED JUNE 2005 The SN74LVCH16901 features independent clock (CLKAB or CLKBA), latch-enable (LEAB or LEBA), and dual 9-bit clock-enable (CLKENAB or CLKENBA) inputs. It also provides parity-enable (SEL) and parity-select (ODD/EVEN) inputs and separate error-signal (ERRA or ERRB) outputs for checking parity. The direction of data flow is controlled by output-enable (OEAB and OEBA) inputs. When SEL is low, the parity functions are enabled. When SEL is high, the parity functions are disabled, and the device acts as an 18-bit registered transceiver. Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators in a mixed 3.3-V/5-V system environment. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. FUNCTION TABLES ABC FUNCTION(1) INPUTS OUTPUT B CLKENAB OEAB LEAB CLKAB A X H X X X Z X L H X L L X L H X H H H L L X X B0(2) L L L ↑ L L L L L ↑ H H L L L L X B0(2) L L L H X B0(3) (1) A-to-B data flow is shown: B-to-A flow is similar, but uses OEBA, LEBA, and CLKENBA. (2) Output level before the indicated steady-state input conditions were established (3) Output level before the indicated steady-state input conditions were established, provided that CLKAB was low before LEAB went low PARITY ENABLE INPUTS OPERATION OR FUNCTION SEL OEBA OEAB L H L Parity is checked on port A and is generated on port B. L L H Parity is checked on port B and is generated on port A. L H H Parity is checked on port B and port A. L L L Parity is generated on port A and B if device is in FF mode. H L L QA data to B, QB data to A Parity functions are disabled; device H L H QB data to A acts as a standard 18-bit registered H H L QA data to B transceiver. H H H Isolation 2 Not Recommended For New Designs |
Numéro de pièce similaire - 74LVCH16901DGGRE4 |
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Description similaire - 74LVCH16901DGGRE4 |
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