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CD54HC297 Fiches technique(PDF) 1 Page - Texas Instruments |
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CD54HC297 Fiches technique(HTML) 1 Page - Texas Instruments |
1 / 15 page 1 Data sheet acquired from Harris Semiconductor SCHS177B CD54HC297, CD74HC297, CD74HCT297 High-Speed CMOS Logic Digital Phase-Locked Loop Features • Digital Design Avoids Analog Compensation Errors • Easily Cascadable for Higher Order Loops • Useful Frequency Range - K-Clock . . . . . . . . . . . . . . . . . . . . . . . . . .DC to 55MHz (Typ) - I/D-Clock . . . . . . . . . . . . . . . . . . . . DC to 35MHz (Typ) • Dynamically Variable Bandwidth • Very Narrow Bandwidth Attainable • Power-On Reset • Output Capability - Standard . . . . . . . . . . . . . . . . . . . . XORPDOUT, ECPDOUT - Bus Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I/DOUT • Fanout (Over Temperature Range) - Standard Outputs . . . . . . . . . . . . . . . . . . 10 LSTTL Loads - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads • Balanced Propagation Delay and Transition Times • Significant Power Reduction Compared to LSTTL Logic ICs • ’HC297 Types - Operation Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 to 6V - High Noise Immunity NIL = 30%, NIH = 30% of VCC at 5V • CD74HCT297 Types - Operation Voltage . . . . . . . . . . . . . . . . . . . . . . . . 4.5 to 5.5V - Direct LSTTL Input Logic Compatibility VIL = 0.8V (Max), VIH = 2V (Min) - CMOS Input Compatibility II ≤ 1µA at VOL, VOH Pinout CD54HC297 (CERDIP) CD74HC297, CD74HCT29 (PDIP) TOP VIEW Description The ’HC297 and CD74HCT297 are high-speed silicon gate CMOS devices that are pin-compatible with low power Schot- tky TTL (LSTTL). These devices are designed to provide a simple, cost-effec- tive solution to high-accuracy, digital, phase-locked-loop appli- cations. They contain all the necessary circuits, with the exception of the divide-by-N counter, to build first-order phase-locked-loops. Both EXCLUSIVE-OR (XORPD) and edge-controlled phase detectors (ECPD) are provided for maximum flexibility. The input signals for the EXCLUSIVE-OR phase detector must have a 50% duty factor to obtain the maximum lock-range. Proper partitioning of the loop function, with many of the build- ing blocks external to the package, makes it easy for the designer to incorporate ripple cancellation (see Figure 2) or to cascade to higher order phase-locked-loops. The length of the up/down K-counter is digitally programmable according to the K-counter function table. With A, B, C and D all LOW, the K-counter is disabled. With A HIGH and B, C and D LOW, the K-counter is only three stages long, which widens the bandwidth or capture range and shortens the lock time of the loop. When A, B, C and D are all programmed HIGH, the K-counter becomes seventeen stages long, which narrows the bandwidth or capture range and lengthens the lock time. Real-time control of loop bandwidth by manipulating the A to D inputs can maximize the overall performance of the digital phase-locked-loop. The ’HC297 and CD74HCT297 can perform the classic first order phase-locked-loop function without using analog com- ponents. The accuracy of the digital phase-locked-loop (DPLL) is not affected by VCC and temperature variations but depends solely on accuracies of the K-clock and loop propa- gation delays. 14 15 16 9 13 12 11 10 1 2 3 4 5 7 6 8 B A ENCTR KCP I/DCP D/U GND I/DOUT VCC D φA 2 ECPDOUT XORPDOUT φB φA 1 C Ordering Information PART NUMBER TEMP. RANGE (oC) PACKAGE CD54HC297F3A -55 to 125 16 Ld CERDIP CD74HC297E -55 to 125 16 Ld PDIP CD74HCT297E -55 to 125 16 Ld PDIP November 1997 - Revised May 2003 CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright © 2003, Texas Instruments Incorporated [ /Title (CD74 HC297 , CD74 HCT29 7) /Sub- ject (High- Speed CMOS Logic Digi- tal Phase- Locked |
Numéro de pièce similaire - CD54HC297_14 |
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Description similaire - CD54HC297_14 |
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