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SN74GTLPH1645 Fiches technique(PDF) 2 Page - Texas Instruments |
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SN74GTLPH1645 Fiches technique(HTML) 2 Page - Texas Instruments |
2 / 22 page www.ti.com DESCRIPTION/ORDERING INFORMATION (CONTINUED) SN74GTLPH1645 16-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVER SCES290D – OCTOBER 1999 – REVISED JUNE 2005 This device is fully specified for live-insertion applications using Ioff, power-up 3-state, and BIAS VCC. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down, which prevents driver conflict. The BIAS VCC circuitry precharges and preconditions the B-port input/output connections, preventing disturbance of active data on the backplane during card insertion or removal, and permits true live-insertion capability. This GTLP device features TI-OPC circuitry, which actively limits the overshoot caused by improperly terminated backplanes, unevenly distributed cards, or empty slots during low-to-high signal transitions. This improves signal integrity, which allows adequate noise margin to be maintained at higher frequencies. High-drive GTLP backplane interface devices feature adjustable edge-rate control (ERC). Changing the ERC input voltage between GND and VCC adjusts the B-port output rise and fall times. This allows the designer to optimize system data-transfer rate and signal integrity to the backplane load. Active bus-hold circuitry holds unused or undriven LVTTL data inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended. When VCC is between 0 and 1.5 V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 1.5 V, the output-enable (OE) input should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. ORDERING INFORMATION TA PACKAGE(1) ORDERABLE PART NUMBER TOP-SIDE MARKING TSSOP – DGG Tape and reel SN74GTLPH1645DGGR GTLPH1645 –40 °C to 85°C TVSOP – DGV Tape and reel SN74GTLPH1645DGVR GL45 VFBGA – GQL Tape and reel SN74GTLPH1645GQLR GL45 (1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. 2 |
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