Moteur de recherche de fiches techniques de composants électroniques
Selected language     French  ▼
Nom de la pièce

AM1705DPTPA3 Datasheet(Fiches technique) 9 Page - Texas Instruments

Click here to check the latest version.
Numéro de pièce AM1705DPTPA3
Description  AM1705 ARM® Microprocessor
Télécharger  165 Pages
Scroll/Zoom Zoom In 100% Zoom Out
Fabricant  TI1 [Texas Instruments]
Site Internet

 9 page
background image
A single set of two level page tables stored in main memory is used to control the address translation,
permission checks and memory region attributes for both data and instruction accesses. The MMU uses a
single unified Translation Lookaside Buffer (TLB) to cache the information held in the page tables. The
MMU features are:
Standard ARM architecture v4 and v5 MMU mapping sizes, domains and access protection scheme.
Mapping sizes are:
1MB (sections)
64KB (large pages)
4KB (small pages)
1KB (tiny pages)
Access permissions for large pages and small pages can be specified separately for each quarter of
the page (subpage permissions)
Hardware page table walks
Invalidate entire TLB, using CP15 register 8
Invalidate TLB entry, selected by MVA, using CP15 register 8
Lockdown of TLB entries, using CP15 register 10
Caches and Write Buffer
The size of the Instruction cache is 16KB, Data cache is 16KB. Additionally, the caches have the following
Virtual index, virtual tag, and addressed using the Modified Virtual Address (MVA)
Four-way set associative, with a cache line length of eight words per line (32-bytes per line) and with
two dirty bits in the Dcache
Dcache supports write-through and write-back (or copy back) cache operation, selected by memory
region using the C and B bits in the MMU translation tables
Critical-word first cache refilling
Cache lockdown registers enable control over which cache ways are used for allocation on a line fill,
providing a mechanism for both lockdown, and controlling cache corruption
Dcache stores the Physical Address TAG (PA TAG) corresponding to each Dcache entry in the TAG
RAM for use during the cache line write-backs, in addition to the Virtual Address TAG stored in the
TAG RAM. This means that the MMU is not involved in Dcache write-back operations, removing the
possibility of TLB misses related to the write-back address.
Cache maintenance operations provide efficient invalidation of, the entire Dcache or Icache, regions of
the Dcache or Icache, and regions of virtual memory.
The write buffer is used for all writes to a noncachable bufferable region, write-through region and write
misses to a write-back region. A separate buffer is incorporated in the Dcache for holding write-back for
cache line evictions or cleaning of dirty cache lines. The main write buffer has 16-word data buffer and a
four-address buffer. The Dcache write-back has eight data word entries and a single address entry.
Advanced High-Performance Bus (AHB)
The ARM Subsystem uses the AHB port of the ARM926EJ-S to connect the ARM to the Config bus and
the external memories. Arbiters are employed to arbitrate access to the separate D-AHB and I-AHB by the
Config Bus and the external memories bus.
Embedded Trace Macrocell (ETM) and Embedded Trace Buffer (ETB)
To support real-time trace, the ARM926EJ-S processor provides an interface to enable connection of an
Embedded Trace Macrocell (ETM). The ARM926EJ-S Subsystem in the device also includes the
Embedded Trace Buffer (ETB). The ETM consists of two parts:
Copyright © 2010–2014, Texas Instruments Incorporated
Device Overview
Submit Documentation Feedback
Product Folder Links: AM1705

Html Pages

1  2  3  4  5  6  7  8  9  10  11  12  13  14  15  16  17  18  19  20  21  22  23  24  25  26  27  28  29  30  31  32  33  34  35  36  37  38  39  40  41  42  43  44  45  46  47  48  49  50  51  52  53  54  55  56  57  58  59  60  61  62  63  64  65  66  67  68  69  70  71  72  73  74  75  76  77  78  79  80  81  82  83  84  85  86  87  88  89  90  91  92  93  94  95  96  97  98  99  100   ...More

Datasheet Download

Lien URL

AllDATASHEET vous a-t-il été utile ?   [ DONATE ]  

À propos de Alldatasheet   |   Publicité   |   Contactez-nous   |   Politique de confidentialité   |   Favoris   |   Echange de liens   |   Fabricants
All Rights Reserved ©

Mirror Sites
English :  ,  |   Chinese :  |   German :  |   Japanese :  |   Russian :
Korean :   |   Spanish :  |   French :  |   Italian :  |   Portuguese :  |   Polish :