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AM1705DPTPA3 Fiches technique(PDF) 56 Page - Texas Instruments

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No de pièce AM1705DPTPA3
Description  AM1705 ARM짰 Microprocessor
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Fabricant  TI1 [Texas Instruments]
Site Internet  http://www.ti.com
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AM1705DPTPA3 Fiches technique(HTML) 56 Page - Texas Instruments

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AM1705
SPRS657E – FEBRUARY 2010 – REVISED JUNE 2014
www.ti.com
6.9
EDMA
Table 6-12 is the list of EDMA3 Channel Contoller Registers and Table 6-13 is the list of EDMA3 Transfer
Controller registers.
Table 6-12. EDMA3 Channel Controller (EDMA3CC) Registers
BYTE ADDRESS
ACRONYM
REGISTER DESCRIPTION
0x01C0 0000
PID
Peripheral Identification Register
0x01C0 0004
CCCFG
EDMA3CC Configuration Register
GLOBAL REGISTERS
0x01C0 0200
QCHMAP0
QDMA Channel 0 Mapping Register
0x01C0 0204
QCHMAP1
QDMA Channel 1 Mapping Register
0x01C0 0208
QCHMAP2
QDMA Channel 2 Mapping Register
0x01C0 020C
QCHMAP3
QDMA Channel 3 Mapping Register
0x01C0 0210
QCHMAP4
QDMA Channel 4 Mapping Register
0x01C0 0214
QCHMAP5
QDMA Channel 5 Mapping Register
0x01C0 0218
QCHMAP6
QDMA Channel 6 Mapping Register
0x01C0 021C
QCHMAP7
QDMA Channel 7 Mapping Register
0x01C0 0240
DMAQNUM0
DMA Channel Queue Number Register 0
0x01C0 0244
DMAQNUM1
DMA Channel Queue Number Register 1
0x01C0 0248
DMAQNUM2
DMA Channel Queue Number Register 2
0x01C0 024C
DMAQNUM3
DMA Channel Queue Number Register 3
0x01C0 0260
QDMAQNUM
QDMA Channel Queue Number Register
0x01C0 0284
QUEPRI
Queue Priority Register(1)
0x01C0 0300
EMR
Event Missed Register
0x01C0 0308
EMCR
Event Missed Clear Register
0x01C0 0310
QEMR
QDMA Event Missed Register
0x01C0 0314
QEMCR
QDMA Event Missed Clear Register
0x01C0 0318
CCERR
EDMA3CC Error Register
0x01C0 031C
CCERRCLR
EDMA3CC Error Clear Register
0x01C0 0320
EEVAL
Error Evaluate Register
0x01C0 0340
DRAE0
DMA Region Access Enable Register for Region 0
0x01C0 0348
DRAE1
DMA Region Access Enable Register for Region 1
0x01C0 0350
DRAE2
DMA Region Access Enable Register for Region 2
0x01C0 0358
DRAE3
DMA Region Access Enable Register for Region 3
0x01C0 0380
QRAE0
QDMA Region Access Enable Register for Region 0
0x01C0 0384
QRAE1
QDMA Region Access Enable Register for Region 1
0x01C0 0388
QRAE2
QDMA Region Access Enable Register for Region 2
0x01C0 038C
QRAE3
QDMA Region Access Enable Register for Region 3
0x01C0 0400 - 0x01C0 043C
Q0E0-Q0E15
Event Queue Entry Registers Q0E0-Q0E15
0x01C0 0440 - 0x01C0 047C
Q1E0-Q1E15
Event Queue Entry Registers Q1E0-Q1E15
0x01C0 0600
QSTAT0
Queue 0 Status Register
0x01C0 0604
QSTAT1
Queue 1 Status Register
0x01C0 0620
QWMTHRA
Queue Watermark Threshold A Register
0x01C0 0640
CCSTAT
EDMA3CC Status Register
GLOBAL CHANNEL REGISTERS
0x01C0 1000
ER
Event Register
0x01C0 1008
ECR
Event Clear Register
(1)
On previous architectures, the EDMA3TC priority was controlled by the queue priority register (QUEPRI) in the EDMA3CC memory-
map. However for this device, the priority control for the transfer controllers is controlled by the chip-level registers in the System
Configuration Module. You should use the chip-level registers and not QUEPRI to configure the TC priority.
56
Peripheral Information and Electrical Specifications
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