TPS3836K33QDBVRQ1 datasheet(6/18 Pages) TI1

No de pièce	TPS3836K33QDBVRQ1

Description	NANOPOWER SUPERVIDORY CIRCUITS

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Fabricant	TI1 [Texas Instruments]

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TPS3836E18-Q1 / J25-Q1 / H30-Q1 / L30-Q1 / K33-Q1

TPS3837E18-Q1 / J25-Q1 / L30-Q1 / K33-Q1, TPS3838E18-Q1 / J25-Q1 / L30-Q1 / K33-Q1

NANOPOWER SUPERVISORY CIRCUITS

SGLS141A − DECEMBER 2002 − REVISED JANUARY 2007

6

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

electrical characteristics over recommended operating conditions (unless otherwise noted)

PARAMETER

TEST CONDITION

MIN

TYP

MAX

UNIT

RESET

VDD = 3.3 V,

IOH = −2 mA

V

High level output voltage

RESET

(TPS3836)

VDD = 6 V,

IOH = −3 mA

0.8

×

V

VOH

High-level output voltage

RESET

VDD = 1.8 V,

IOH = −1 mA

0.8

×

VDD

V

RESET

(TPS3837)

VDD = 3.3 V,

IOL = −2 mA

RESET

VDD = 1.8 V,

IOL = 1 mA

V

Low level output voltage

RESET

(TPS3836/8)

VDD = 3.3 V,

IOL = 2 mA

04

V

VOL

Low-level output voltage

RESET

VDD = 3.3 V,

IOL = 2 mA

0.4

V

RESET

(TPS3837)

VDD = 6 V,

IOL = 3 mA

Power up reset voltage

TPS3836/8

VDD ≥ 1.1 V,

IOL = 50 µA

0.2

Power-up reset voltage

(see Note 2)

TPS3837

VDD ≥ 1.1 V,

IOH = −50 µA

0.8

×

VDD

V

TPS383xE18

1.64

1.71

1.76

Nti

i

it th

h ld

TPS383xJ25

2.16

2.25

2.30

VIT

Negative-going input threshold

voltage (see Note 3)

TPS383xH30

2.70

2.79

2.85

V

VIT

voltage (see Note 3)

TPS383xL30

2.54

2.64

2.71

V

TPS383xK33

2.82

2.93

3.10

1.7 V < VIT < 2.5 V

30

Vhys

Hysteresis at VDD input

2.5 V

< VIT < 3.5 V

40

mV

Vhys

Hysteresis at VDD input

3.5 V < VIT < 5 V

50

mV

IIH

High-level input current

MR

(see Note 4)

MR = 0.7

× VDD,

VDD = 6 V

−40

−60

−100

µA

IIH

High level input current

CT

CT = VDD = 6 V

−25

25

nA

IIL

Low-level input current

MR

(see Note 4)

MR = 0 V,

VDD = 6 V

−130

−200

−340

µA

IIL

Low level input current

CT

CT = 0 V,

VDD = 6 V

−25

25

nA

IOH

High-level output current

TPS3838

VDD = VIT + 0.2 V,

VOH = VDD

25

nA

VDD > VIT,

VDD < 3 V

220

500

nA

IDD

Supply current

VDD > VIT,

VDD > 3 V

250

550

nA

IDD

Supply current

VDD < VIT

10

25

µA

Internal pullup resistor at MR

30

k

Ω

CI

Input capacitance at MR, CT

VI = 0 V to VDD

5

pF

NOTES:

2. The lowest voltage at which RESET output becomes active. tr, VDD ≥ 15 µs/V

3. To ensure best stability of the threshold voltage, a bypass capacitor (ceramic, 0.1

µF) should be placed near the supply terminal.

4. If manual reset is unused, MR should be connected to VDD to minimize current consumption.

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