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DM54LS25 Fiches technique(PDF) 1 Page - National Semiconductor (TI) |
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DM54LS25 Fiches technique(HTML) 1 Page - National Semiconductor (TI) |
1 / 6 page TLF6418 May 1992 DM54LS259DM74LS259 8-Bit Addressable Latches General Description These 8-bit addressable latches are designed for general purpose storage applications in digital systems Specific uses include working registers serial-holding registers and active-high decoders or demultiplexers They are multifunc- tional devices capable of storing single-line data in eight addressable latches and being a 1-of-8 decoder or demulti- plexer with active-high outputs Four distinct modes of operation are selectable by control- ling the clear and enable inputs as enumerated in the func- tion table In the addressable-latch mode data at the data- in terminal is written into the addressed latch The ad- dressed latch will follow the data input with all unaddressed latches remaining in their previous states In the memory mode all latches remain in their previous states and are unaffected by the data or address inputs To eliminate the possibility of entering erroneous data in the latches the en- able should be held high (inactive) while the address lines are changing In the 1-of-8 decoding or demultiplexing mode the addressed output will follow the level of the D input with all other outputs low In the clear mode all out- puts are low and unaffected by the address and data inputs Features Y 8-Bit parallel-out storage register performs serial-to-par- allel conversion with storage Y Asynchronous parallel clear Y Active high decoder Y Enabledisable input simplifies expansion Y Direct replacement for Fairchild 9334 Y Expandable for N-bit applications Y Four distinct functional modes Y Typical propagation delay times Enable-to-output 18 ns Data-to-output 16 ns Address-to-output 21 ns Clear-to-output 17 ns Y Fan-out IOL (sink current) 54LS259 4 mA 74LS259 8 mA IOH (source current) b04 mA Y Typical ICC 22 mA Connection Diagram Dual-In-Line Package TLF6418 – 1 Order Number DM54LS259E DM54LS259J DM54LS259W DM74LS259M DM74LS259WM or DM74LS259N See NS Package Number E20A J16A M16A M16B N16E or W16A Function Table Inputs Output of Each Addressed Other Function Clear E Latch Output HL D Qi0 Addressable Latch HH Qi0 Qi0 Memory L L D L 8-Line Demultiplexer L H L L Clear Latch Selection Table Select Inputs Latch CB A Addressed LLL 0 LL H 1 LHL 2 LH H 3 HL L 4 HLH 5 HH L 6 HHH 7 H e High Level L e Low Level D e the Level of the Data Input Qi0 e the Level of Qi (i e 0 1 7 as Appropriate) before the Indicated Steady-State Input Conditions Were Established C1995 National Semiconductor Corporation RRD-B30M105Printed in U S A |
Numéro de pièce similaire - DM54LS25 |
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Description similaire - DM54LS25 |
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