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ADC08831IM Fiches technique(PDF) 4 Page - Texas Instruments |
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ADC08831IM Fiches technique(HTML) 4 Page - Texas Instruments |
4 / 32 page ADC08831, ADC08832 SNAS015C – SEPTEMBER 1999 – REVISED MARCH 2013 www.ti.com Electrical Characteristics (continued) The following specifications apply for VCC = VREF = +5VDC, and fCLK = 2 MHz unless otherwise specified. Boldface limits apply for TA = TJ = TMIN to TMAX; all other limits TA = TJ = 25°C. Symbol Parameter Conditions Typical(1) Limits(2) Units (Limits) IOUT TRI-STATE Output Current VOUT = 0V −3.0 μA (max) VOUT = 5V 3.0 μA (max) ISOURCE Output Source Current VOUT = 0V −6.5 mA (max) ISINK Output Sink Current VOUT = VCC 8.0 mA (min) ICC Supply Current ADC08831 CLK = VCC CS = VCC 0.6 1.0 mA (max) CS = LOW 1.7 2.4 mA (max) ICC Supply Current ADC08832 CLK = CS = VCC 1.3 1.8 mA (max) VCC (8) CS = LOW 2.4 3.5 mA (max) (8) For the ADC08832 Vref is internally tied to VCC, therefore, for the ADC08832 reference current is included in the supply current. Electrical Characteristics The following specifications apply for VCC = VREF = +5 VDC, and tr = tf = 20 ns unless otherwise specified. Boldface limits apply for TA = TJ = TMIN to TMAX; all other limits TA = TJ = 25°C. Symbol Parameter Conditions Typical(1) Limits(2) Units (Limits) fCLK Clock Frequency 2 MHz (max) Clock Duty Cycle(3) 40 % (min) 60 % (max) TC Conversion Time (Not Including MUX fCLK = 2MHz 8 1/fCLK (max) Addressing Time) 4 μs (max) tCA Acquisition Time ½ 1/fCLK (max) tSET-UP CS Falling Edge or Data Input 25 ns (min) Valid to CLK Rising Edge tHOLD Data Input Valid after CLK 20 ns (min) Rising Edge tpd1, tpd0 CLK Falling Edge to Output Data Valid(4) CL = 100 pF: Data MSB First 250 ns (max) Data LSB First 200 ns (max) t1H, t0H TRI-STATE Delay from Rising Edge CL = 10 pF, RL = 10 kΩ 50 ns of CS to Data Output and SARS Hi-Z (see TRI-STATE Test Circuits and Waveforms) CL = 100 pF, RL = 2 kΩ 180 ns (max) CIN Capacitance of Analog Input(5) 13 pF CIN Capacitance of Logic Inputs 5 pF COUT Capacitance of Logic Outputs 5 pF (1) Typicals are at TJ = 25°C and represent the most likely parametric norm. (2) Specified to TI's AOQL (Average Outgoing Quality Level). (3) A 40% to 60% duty cycle range insures proper operation at all clock frequencies. In the case that an available clock has a duty cycle outside of these limits the minimum time the clock is high or low must be at least 250 ns. The maximum time the clock can be high or low is 60 μs. (4) Since data, MSB first, is the output of the comparator used in the successive approximation loop, an additional delay is built in to allow for comparator response time. (5) Analog inputs are typically 300 ohms input resistance to a 13pF sample and hold capacitor. 4 Submit Documentation Feedback Copyright © 1999–2013, Texas Instruments Incorporated Product Folder Links: ADC08831 ADC08832 |
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