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ADC08DL500 Fiches technique(PDF) 4 Page - Texas Instruments |
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ADC08DL500 Fiches technique(HTML) 4 Page - Texas Instruments |
4 / 57 page GND VA 50k 50k 200k 8 pF GND VA GND VA 50k 50k 200k 8 pF VA SDATA DDR ADC08DL500 SNAS495C – MARCH 2011 – REVISED MARCH 2011 www.ti.com Pin Functions Pin No. Symbol Equivalent Circuit Description DCLK Edge Select, Double Data Rate Enable and Serial Data Input. This input sets the output edge of DCLK+ at which the OutEdge / DDR / output data transitions. When this pin is floating or connected 6 SDATA to 1/2 the supply voltage, DDR clocking is enabled. When the extended control mode is enabled, this pin functions as the SDATA input. OutEdge functionality: (2) DCLK Reset. When single-ended DCLK_RST is selected by floating or setting pin 58 logic high, a positive pulse on this pin is used to reset and synchronize the DCLK outputs of DCLK_RST / multiple converters. When differential DCLK_RST is selected 17 DCLK_RST+ by setting pin 58 logic low, this pin receives the positive polarity of a differential pulse signal used to reset and synchronize the DCLK outputs of multiple converters. DCLK_RST, DCLK_RST+ functionality: (3) Power Down Pins. A logic high on the PD pin puts the entire 28 PD device into the Power Down Mode. PD functionality: (3) Calibration Cycle Initiate. A minimum tCAL_L input clock cycles 32 CAL logic low followed by a minimum of tCAL_H input clock cycles high on this pin initiates the calibration sequence. Full Scale Range Select, Alternate Extended Control Enable and DCLK_RST-. This pin has three functions. It can conditionally control the ADC full-scale voltage, enable the extended control mode, or become the negative polarity signal of a differential pair in differential DCLK_RST mode. If pin 58 and pin 47 are floating or at logic high, this pin can be used to set the full-scale-range or can be used as an alternate extended control enable pin . When used as the FSR pin, a logic low on this pin sets the full-scale differential FSR/ALT_ECE/DC input range to a reduced VIN input level. A logic high on this 16 LK_RST- pin sets the full-scale differential input range to a higher VIN input level. To enable the extended control mode, whereby the serial interface and control registers are employed, allow this pin to float or connect it to a voltage equal to VA/2. Note that pin 47 overrides the extended control enable of this pin. When pin 58 is held at logic low, this pin acts as the DCLK_RST- pin. When in differential DCLK_RST mode, there is no pin-controlled FSR and the full-scale-range is defaulted to the higher VIN input level. FSR, ALT_ECE, DCLK_RST- functionality: (3) (2) This pin/bit functionality is not tested in production test; performance is tested in the specified/default mode only. (3) This pin/bit functionality is not tested in production test; performance is tested in the specified/default mode only. 4 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Links: ADC08DL500 |
Numéro de pièce similaire - ADC08DL500_15 |
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Description similaire - ADC08DL500_15 |
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