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Moteur de recherche de fiches techniques de composants électroniques |
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Moteur de recherche de fiches techniques de composants électroniques |
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ADC1175-50 Fiches technique(PDF) 6 Page - Texas Instruments |
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ADC1175-50 Fiches technique(HTML) 6 Page - Texas Instruments |
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6 / 27 page  ADC1175-50 SNAS027G – JANUARY 2000 – REVISED APRIL 2013 www.ti.com CONVERTER ELECTRICAL CHARACTERISTICS The following specifications apply for AVDD = DVDD = +5.0 VDC, PD = 0V, VRT = +2.6V, VRB = 0.6V, CL = 20 pF, fCLK = 50 MHz at 50% duty cycle. Boldface limits apply for TA = TMIN to TMAX; all other limits TA = 25°C (1) (2). Units Symbol Parameter Conditions Typical(3) Limits(3) (Limits) DC ACCURACY INL Integral Non Linearity Error VIN = 0.6V to 2.6V ±0.8 ±1.95 LSB (max) +0.7 +1.75 LSB (max) DNL Differential Non-Linearity VIN = 0.6V to 2.6V −0.7 −1.0 LSB (min) Resolution for No Missing 8 Bits Codes EOT Top Offset Voltage −12 mV EOB Bottom Offset Voltage +10 mV VIDEO ACCURACY DP Differential Phase Error fIN = 4.43 MHz Modulated Ramp 0.5 deg DG Differential Gain Error fIN = 4.43 MHz Modulated Ramp 1.0 % ANALOG INPUT AND REFERENCE CHARACTERISTIC VRB V (min) VIN Input Range 2.0 VRT V (max) (CLK LOW) 4 pF VIN = 1.5V CIN VIN Input Capacitance +0.7 Vrms (CLK HIGH) 7 pF RIN RIN Input Resistance >1 M Ω BW Full Power Bandwidth 120 MHz RRT Top Reference Resistor 320 Ω 200 Ω (min) RREF Reference Ladder Resistance VRT to VRB 270 350 Ω (max) RRB Bottom Reference Resistor 80 Ω 5.4 mA (min) VRT = VRTS, VRB = VRBS 7 10.8 mA (max) IREF Reference Ladder Current 6.1 mA (min) VRT = VRTS, VRB = AVSS 8 12.3 mA (max) Reference Top Self Bias VRT Connected to VRTS, V (min) VRT 2.6 Voltage VRB Connected to VRBS V (max) Reference Bottom Self Bias VRT Connected to VRTS, 0.55 V (min) VRB 0.6 Voltage VRB Connected to VRBS 0.70 V (max) (1) The analog inputs are protected as shown below. Input voltage magnitudes up to 6.5V or 500 mV below GND will not damage this device. However, errors in the A/D conversion can occur if the input goes above VDD or below GND by more than 50 mV. As an example, if AVDD is 4.75 VDC, the full-scale input voltage must be ≤4.80 VDC to ensure accurate conversions. spacer (2) To ensure accuracy, it is required that AVDD and DVDD be well bypassed. Each VDD pin must be decoupled with separate bypass capacitors. (3) Typical figures are at TJ = 25°C, and represent most likely parametric norms. Test limits are ensured to TI's AOQL (Average Outgoing Quality Level). 6 Submit Documentation Feedback Copyright © 2000–2013, Texas Instruments Incorporated Product Folder Links: ADC1175-50 |
Numéro de pièce similaire - ADC1175-50 |
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Description similaire - ADC1175-50 |
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