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ADC081000 Fiches technique(PDF) 10 Page - Texas Instruments |
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ADC081000 Fiches technique(HTML) 10 Page - Texas Instruments |
10 / 41 page ADC081000 SNAS209G – FEBRUARY 2004 – REVISED MAY 2013 www.ti.com CONVERTER ELECTRICAL CHARACTERISTICS (continued) The following specifications apply after calibration for VA = VDR = +1.9VDC, OutV = 1.9V, VIN FSR (a.c. coupled) = differential 800mVP-P, CL = 10 pF, Differential, a.c. coupled Sinewave Clock, fCLK = 1 GHz at 0.5VP-P with 50% duty cycle, REXT = 3300Ω ± 0.1%, Analog Signal Source Impedance = 100 Ω. Boldface limits apply for TA = TMIN to TMAX. All other limits TA = 25°C, unless otherwise stated (1)(2)(3) Units Symbol Parameter Conditions Typical(4) Limits(4) (Limits) CLOCK INPUT CHARACTERISTICS 0.4 VP-P (min) Square Wave Clock 0.6 2.0 VP-P (max) VID Differential Clock Input Level 0.4 VP-P (min) Sine Wave Clock 0.6 2.0 VP-P (max) II Input Current VIN = 0V or VIN = VA ±1 µA Differential 0.02 pF CIN Input Capacitance(7) Each Input to Ground 1.5 pF DIGITAL CONTROL PIN CHARACTERISTICS VIH Logic High Input Voltage See(8) 1.4 V (min) VIL Logic Low Input Voltage See(8) 0.5 V (max) II Input Current VIN = 0 or VIN = VA ±1 µA CIN Logic Input Capacitance(9) Each input to ground 1.2 pF DIGITAL OUTPUT CHARACTERISTICS 200 mVP-P (min) OutV = VA, measured single-ended 300 450 mVP-P (max) VOD LVDS Differential Output Voltage 140 mVP-P (min) OutV = GND, measured single-ended 225 340 mVP-P (max) Change in LVDS Output Swing Δ VOD DIFF ±1 mV Between Logic Levels VOS Output Offset Voltage 800 mV Output Offset Voltage Change Between Δ VOS ±1 mV Logic Levels IOS Output Short Circuit Current Output+ & Output- connected to 0.8V −4 mA ZO Differential Output Impedance 100 Ohms POWER SUPPLY CHARACTERISTICS PD = Low 646 792 mA (max) IA Analog Supply Current PD = High 4.5 mA PD = Low 108 160 mA (max) IDR Output Driver Supply Current PD = High 0.1 mA PD = Low 1.43 1.8 W (max) PD Power Consumption PD = High 8.7 mW Change in Offset Error with change in PSRR1 D.C. Power Supply Rejection Ratio 73 dB VA from 1.8V to 2.0V AC ELECTRICAL CHARACTERISTICS TA = 85°C 1.1 1.0 GHz (min) fCLK1 Maximum Conversion Rate TA ≤ 75°C 1.3 GHz TA ≤ 70°C 1.6 GHz fCLK2 Minimum Conversion Rate 200 MHz 200 MHz ≤ Input clock frequency < 1 20 % (min) Input Clock Duty Cycle 50 GHz 80 % (max) tCL Input Clock Low Time(8) 500 200 ps (min) (7) The analog and clock input capacitances are die capacitances only. Additional package capacitances of 0.65 pF differential and 0.95 pF each pin to ground are isolated from the die capacitances by lead and bond wire inductances. (8) This parameter is specified by design and characterization and is not tested in production. (9) The digital control pin capacitances are die capacitances only. Additional package capacitance of 1.6 pF each pin to ground are isolated from the die capacitances by lead and bond wire inductances. 10 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated Product Folder Links: ADC081000 |
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