OBSOLETE

54AC175, 54ACT175

SNOS094B – AUGUST 1998 – REVISED APRIL 2013

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Connection Diagrams

Figure 3. Pin Assignment for CDIP and CLGA

Figure 4. Pin Assignment for LCCC

See Package Numbers NFE and NAD

See Package Number NAJ

Functional Description

The 'AC/'ACT175 consists of four edge-triggered D flip-flops with individual D inputs and Q and Q outputs. The

Clock and Master Reset are common. The four flip-flops will store the state of their individual D inputs on the

LOW-to-HIGH clock (CP) transition, causing individual Q and Q outputs to follow. A LOW input on the Master

Reset (MR) will force all Q outputs LOW and Q outputs HIGH independent of Clock or Data inputs. The

'AC/'ACT175 is useful for general logic applications where a common Master Reset and Clock are acceptable.

TRUTH TABLE

(1)

Inputs

Outputs

L

L

H

H

H

L

(1)

H = HIGH Voltage Level

L = LOW Voltage Level

LOGIC DIAGRAM

Please note that this diagram is provided only for the understanding of logic operations and should not be used to

estimate propagation delays.

2

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Product Folder Links: 54AC175 54ACT175