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CS1112YDWF24 Fiches technique(PDF) 3 Page - ON Semiconductor |
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CS1112YDWF24 Fiches technique(HTML) 3 Page - ON Semiconductor |
3 / 12 page CS1112 http://onsemi.com 3 ELECTRICAL CHARACTERISTICS (9.0 V < VPWR < 17 V, 4.5 V < VDD < 5.5 V, –40°C < TJ < 125°C, 5.5 V < VPWR < 25 V, (Outputs Functional); unless otherwise specified.) Characteristic Test Conditions Min Typ Max Unit Supply Voltages and Currents VDD Power On Reset Threshold Outputs Latched Off By Event 2.5 3.0 3.5 V VDD Power On Reset Hysteresis – – 200 – mV VPWR Undervoltage Outputs Latched Off By Event 4.0 4.5 5.0 V VPWR Overvoltage Lockout Outputs Latched Off By Event 30 35 45 V Digital Supply Current, IV(DD) All Outputs On (@ 350 mA) – – 5.0 mA Analog Supply Current, IV(PWR) All Outputs On (@ 350 mA) – – 5.0 mA Sleep Current, IV(PWR) VDD ≤ 0.5 V – – 10 µA Digital Inputs and Outputs VIN High SI, SCLK, CSB, IN0, IN1, IN2, IN3 70 – – %VDD VIN Low SI, SCLK, CSB, IN0, IN1, IN2, IN3 – – 30 %VDD VIN Hysteresis – – 230 – mV Input Pulldown Current SI, IN0, IN1, IN2, IN3, VIN = 30% VDD – – 25 µA Input Pullup Current CSB, VIN = 70% VDD – – –25 µA Status Low ISTATUS = 0.5 mA – 0.1 0.5 V Fault Detection/Timing Overcurrent Sense Time, tSS Overcurrent Sense Time, ROSC = 82 kΩ 25 62.5 100 µs Overcurrent Shutdown Time Overcurrent Shutdown Time, ROSC = 82 kΩ 1.60 3.94 6.3 ms Fault Duty Cycle After the first fault cycle, Note 1. 1.4 1.56 1.7 % Open Load Trip Point IN = Low 40 50 60 %VDD Open Load Sense Time Open Load Sense Time, ROSC = 82 kΩ 12.5 – 100 µs Power Outputs VDRAIN Clamp ID = 20 mA, tCLAMP = 100 µs 48 52 64 V Drain Leakage Current VDRAIN = 17 V – – 25 µA Drain Leakage Current VDRAIN = 46 V – – 400 µA RDS(ON) VPWR = 13 V, ID = 0.5 A – 1.0 2.0 Ω Current Limit Note 2. 3.0 4.5 6.0 A Reverse Diode Drop Reverse Diode Drop I = 350 mA – – 1.4 V Fall Time Delay, tphl VPWR = 13 V, RLOAD = 33 Ω, Note 3. (see Figure 2) – – 10 µs Rise Time Delay, tplh VPWR = 13 V, RLOAD = 33 Ω, Note 3. (see Figure 2) – – 15 µs Rise Time, tr VPWR = 13 V, RLOAD = 33 Ω 0.4 – 10 µs Fall Time, tf VPWR = 13 V, RLOAD = 33 Ω 0.4 – 10 µs 1. Guaranteed by design. 2. A duty cycle mode will initiate at a minimum of 1.0 A and before the current limit. 3. Output turn on delay and turn off delay from rising edge of CSB to the output reaching 50% of VPWR. |
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