Moteur de recherche de fiches techniques de composants électroniques |
|
TSC2102IDA Fiches technique(PDF) 8 Page - Texas Instruments |
|
|
TSC2102IDA Fiches technique(HTML) 8 Page - Texas Instruments |
8 / 54 page TSC2102 SLAS379A− APRIL 2003 − REVISED JUNE 2004 www.ti.com 8 AUDIO INTERFACE TIMING DIAGRAMS ts (DI) th(DI) LRCK BCLK DIN td(WS) Figure 1. I2S/LJF/RJF Timing in Master Mode TYPICAL TIMING REQUIREMENTS All specifications at 25 °C, IOVDD = 3.3 V, DVDD = 1.8 V(1) PARAMETER MIN MAX UNITS td (WS) LRCK delay 15 ns ts(DI) DIN setup 6 ns th(DI) DIN hold 6 ns tr Rise time 6 ns tf Fall time 6 ns (1) These parameters are based on characterization and are not tested in production. ts (DI) th(DI) LRCK BCLK DIN td(WS) td(WS) Figure 2. DSP Timing in Master Mode TYPICAL TIMING REQUIREMENTS All specifications at 25 °C, IOVDD = 3.3 V, DVDD = 1.8 V(1) PARAMETER MIN MAX UNITS td (WS) LRCK delay 15 ns ts(DI) DIN setup 6 ns th(DI) DIN hold 6 ns tr Rise time 6 ns tf Fall time 6 ns (1) These parameters are based on characterization and are not tested in production. |
Numéro de pièce similaire - TSC2102IDA |
|
Description similaire - TSC2102IDA |
|
|
Lien URL |
Politique de confidentialité |
ALLDATASHEET.FR |
ALLDATASHEET vous a-t-il été utile ? [ DONATE ] |
À propos de Alldatasheet | Publicité | Contactez-nous | Politique de confidentialité | Echange de liens | Fabricants All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |