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DAC0854BIWM Fiches technique(PDF) 4 Page - National Semiconductor (TI) |
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DAC0854BIWM Fiches technique(HTML) 4 Page - National Semiconductor (TI) |
4 / 14 page Converter Electrical Characteristics (Continued) The following specifications apply for AVCC e DVCC e 5V VREF e 265V VBIAS e 14V RL e 2kX (RL is the load resistor on the analog outputs – pins 1 11 14 and 19) and fCLK e 10 MHz unless otherwise specified Boldface limits apply for TA e TJ from TMIN to TMAX All other limits apply for TA e 25 C Symbol Parameter Conditions Typical Limit Units (Note 3) (Note 4) (Limits) AC ELECTRICAL CHARACTERISTICS (Continued) tCZ1 Output Hi-Z to Valid 1 37 ns (max) tCZ0 Output Hi-Z to Valid 0 42 ns (max) t1H CS to Output Hi-Z 10 kX with 60 pF 130 ns (max) t0H CS to Output Hi-Z 10 kX with 60 pF 117 ns (max) Note 1 Absolute Maximum Ratings indicate limits beyond which damage to the device may occur Operating Ratings indicate conditions for which the device is functional These ratings do not guarantee specific performance limits however For guaranteed specifications and test conditions see the Converter Electrical Characteristics The guaranteed specifications apply only for the test conditions listed Some performance characteristics may degrade when the device is not operated under the listed test conditions Note 2 All voltages are measured with respect to ground unless otherwise specified Note 3 When the input voltage (VIN) at any pin exceeds the power supply rails (VIN k GND or VIN l Va) the absolute value of current at that pin should be limited to 5 mA or less Note 4 The sum of the currents at all pins that are driven beyond the power supply voltages should not exceed 20 mA Note 5 The maximum power dissipation must be derated at elevated temperatures and is dictated by TJmax (maximum junction temperature) HJA (package junction to ambient thermal resistance) and TA (ambient temperature) The maximum allowable power dissipation at any temperature is PDmax e (TJmax b TA) HJA or the number given in the Absolute Maximum Ratings whichever is lower The table below details TJmax and HJA for the various packages and versions of the DAC0854 Part Number TJmax ( C) HJA ( CW) DAC0854BIN DAC0854CIN 125 46 DAC0854BIJ DAC0854CIJ 125 53 DAC0854BIWM DAC0854CIWM 125 64 DAC0854CMJ883 150 53 Note 6 Human body model 100 pF discharged through a 15 kX resistor Note 7 See AN450 ‘‘Surface Mounting Methods and Their Effect on Production Reliability’’ of the section titled ‘‘Surface Mount’’ found in any current Linear Databook for other methods of soldering surface mount devices Note 8 Typicals are at TJ e 25 C and represent most likely parametric norm Note 9 Limits are guaranteed to National’s AOQL (Average Outgoing Quality Level) Note 10 A monotonicity of 8 bits for the DAC0854 means that the output voltage changes in the same direction (or remains constant) for each increase in the input code Note 11 Integral linearity error is the maximum deviation of the output from the line drawn between zero and full-scale (excluding the effects of zero error and full- scale error) Note 12 Full-scale error is measured as the deviation from the ideal 2800V full-scale output when VREF e 2650V and VBIAS e 1400V Note 13 Full-scale error tempco and zero error tempco are defined by the following equation Error tempco e Error (TMAX) b Error (TMIN) VSPAN ( 106 TMAX b TMIN ( where Error (TMAX) is the zero error or full-scale error at TMAX (in volts) and Error (TMIN) is the zero error or full-scale error at TMIN (in volts) VSPAN is the output voltage span of the DAC0854 which depends on VBIAS and VREF Note 14 Zero error is measured as the deviation from the ideal 0310V output when VREF e 2650V VBIAS e 1400V and the digital input word is all zeros Note 15 Power Supply Sensitivity is the maximum change in the offset error or the full-scale error when the power supply differs from its optimum 5V by up to 025V (5%) The load resistor RL e 5kX Note 16 Positive or negative settling time is defined as the time taken for the output of the DAC to settle to its final full-scale or zero output to within g05 LSB This time shall be referenced to the 50% point of the positive edge of CS which initiates the update of the analog outputs Note 17 Digital crosstalk is the glitch measured on the output of one DAC while applying an all 0s to all 1s transition at the input of the other DACs Note 18 All DACs have full-scale outputs latched and DI is clocked with no update of the DAC outputs The glitch is then measured on the DAC outputs Note 19 Clock feedthrough is measured for each DAC with its output at full-scale The serial clock is then applied to the DAC at a frequency of 10 MHz and the glitch on each DAC full-scale output is measured Note 20 Channel-to-channel isolation is a measure of the effect of a change in one DAC’s output on the output of another DAC The VREF of the first DAC is varied between 14V and 265V at a frequency of 15 kHz while the change in full-scale output of the second DAC is measured The first DAC is loaded with all 0s Note 21 Glitch energy is the difference between the positive and negative glitch areas at the output of the DAC when a 1 LSB digital input code change is applied to the input The glitch energy will have its largest value at one of the three major transitions The peak value of the maximum glitch is separately specified Note 22 Power Supply Rejection Ratio is measured by varying AVCC e DVCC between 475V and 525V with a frequency of 10 kHz and measuring the proportion of this signal imposed on a full-scale output of the DAC under consideration Note 23 The bandgap reference tempco is defined by the following equation Tempco e VREF (TMAX) b VREF (TMIN) VREF (TROOM) ( 106 TMAX b TMIN ( where TROOM e 25 C VREF (TMAX) is the reference output at TMAX and similarly for VREF (TMIN) and VREF (TROOM) Note 24 A Military RETS specification is available upon request 4 |
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