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FM25V02A-G Fiches technique(PDF) 3 Page - Cypress Semiconductor |
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FM25V02A-G Fiches technique(HTML) 3 Page - Cypress Semiconductor |
3 / 23 page FM25V02A Document Number: 001-90865 Rev. *F Page 3 of 23 Pinouts Figure 1. 8-pin SOIC Pinout Figure 2. 8-pin DFN Pinout Pin Definitions Pin Name I/O Type Description SCK Input Serial Clock. All I/O activity is synchronized to the serial clock. Inputs are latched on the rising edge and outputs occur on the falling edge. Because the device is synchronous, the clock frequency may be any value between 0 and 40 MHz and may be interrupted at any time. CS Input Chip Select. This active LOW input activates the device. When HIGH, the device enters the low-power standby mode, ignores other inputs, and the output is tristated. When LOW, the device internally activates the SCK signal. A falling edge on CS must occur before every opcode. SI[1] Input Serial Input. All data is input to the device on this pin. The pin is sampled on the rising edge of SCK and is ignored at other times. It should always be driven to a valid logic level to meet IDD specifica- tions. SO[1] Output Serial Output. This is the data output pin. It is driven during a read and remains tristated at all other times including when HOLD is LOW. Data transitions are driven on the falling edge of the serial clock. WP Input Write Protect. This active LOW pin prevents write operation to the Status Register when WPEN is set to ‘1’. This is critical because other write protection features are controlled through the Status Register. A complete explanation of write protection is provided on Status Register and Write Protection on page 7. This pin must be tied to VDD if not used. HOLD Input HOLD Pin. The HOLD pin is used when the host CPU must interrupt a memory operation for another task. When HOLD is LOW, the current operation is suspended. The device ignores any transition on SCK or CS. All transitions on HOLD must occur while SCK is LOW. This pin has a weak internal pull-up (refer to the RIN spec in DC Electrical Characteristics). VSS Power supply Ground for the device. Must be connected to the ground of the system. VDD Power supply Power supply input to the device. EXPOSED PAD No connect The EXPOSED PAD on the bottom of 8-pin DFN package is not connected to the die. The EXPOSED PAD should not be soldered on the PCB. HOLD SCK 1 2 3 4 5 CS 8 7 6 VDD SI SO Top View not to scale VSS WP SO CS VSS WP SI VDD SCK HOLD 1 2 45 6 7 8 3 O PAD EXPOSED Top View not to scale Note 1. SI may be connected to SO for a single pin data interface . |
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