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SN74CBTLV3257PWR Fiches technique(PDF) 7 Page - Texas Instruments |
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SN74CBTLV3257PWR Fiches technique(HTML) 7 Page - Texas Instruments |
7 / 28 page 1B1 1A OE 1B2 SW SW 2B1 2A 2B2 SW SW 3B1 3A 3B2 SW SW 4B1 4A 4B2 SW SW S 4 7 9 12 1 15 2 3 5 6 11 10 14 13 SN74CBTLV3257 www.ti.com SCDS040K – DECEMBER 1997 – REVISED APRIL 2015 8 Detailed Description 8.1 Overview The SN74CBTLV3257 device is a 4-bit 1-of-2 high-speed FET multiplexer and demultiplexer. The low ON- state resistance of the switch allows connections to be made with minimal propagation delay. The select (S) input controls the data flow. The FET multiplexers and demultiplexers are disabled when the output-enable (OE) input is high. This device is fully specified for partial-power-down applications using Ioff. The Ioff feature ensures that damaging current will not backflow through the device when it is powered down. The device has isolation during power off. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. 8.2 Functional Block Diagram 8.3 Feature Description The SN74CBTLV3257 features 5- Ω switch connection between ports, allowing for low signal loss across the switch. Rail-to-rail switching on data I/O allows for full voltage swing outputs. Ioff supports partial-power-down mode operation, protecting the chip from voltages at output ports when it is not powered on. Latch-up performance exceeds 100 mA per JESD 78, Class II. 8.4 Device Functional Modes Table 1. Function Table INPUTS FUNCTION OE S L L A port = B1 port L H A port = B2 port H X Disconnect Copyright © 1997–2015, Texas Instruments Incorporated Submit Documentation Feedback 7 Product Folder Links: SN74CBTLV3257 |
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