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SN74CBT3383DBR Fiches technique(PDF) 10 Page - Texas Instruments |
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SN74CBT3383DBR Fiches technique(HTML) 10 Page - Texas Instruments |
10 / 26 page 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Time - ns Input Output C001 SN74CBT3383, SN54CBT3383 SCDS003P – NOVEMBER 1992 – REVISED DECEMBER 2015 www.ti.com Typical Application (continued) 9.2.2 Detailed Design Procedure The 2-bit bus is connected directly to the 1A1, 1A2 on the SN74CBT3383, which essentially combines in the bus controller to form a single input or split bus bits. When BE is low and BX is low, the selected bus is using 1A1 and 1B1 as inputs and outputs. This means that Device 1 is connected to the bus controller and Device 2 is connected to Device 3 when BE is low and BX is low. While keeping BE low and using BX high, we can enable communication from the bus controller to Device 2 and from Device 1 to Device 3. This setup is especially useful when two controllers or devices need to share the same data from Device 1 and Device 2 and the bus addresses are limited or hard coded. The 0.1- μF capacitor on VCC is a decoupling capacitor and should be placed as close as possible to the device. 9.2.3 Application Curve VCC = 4.5 V Figure 4. Propagation Delay (tpd) Simulation Results 10 Submit Documentation Feedback Copyright © 1992–2015, Texas Instruments Incorporated Product Folder Links: SN74CBT3383 SN54CBT3383 |
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