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SN74CB3T3306DCTR Fiches technique(PDF) 1 Page - Texas Instruments |
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SN74CB3T3306DCTR Fiches technique(HTML) 1 Page - Texas Instruments |
1 / 19 page A EN(2) B Control Circuit VG(1) (1) Gate voltage (VG) is approximately equal to VCC + VT when the switch is ON and VI > VCC + VT. (2) EN is the internal enable signal applied to the switch. Product Folder Sample & Buy Technical Documents Tools & Software Support & Community SN74CB3T3306 SCDS119C – JANUARY 2003 – REVISED DECEMBER 2015 SN74CB3T3306 Dual FET Bus Switch 2.5-V/3.3-V Low-Voltage Bus Switch With 5-V Tolerant Level Shifter 1 Features 2 Applications 1 • Output Voltage Translation Tracks VCC • Supports Digital Applications: • Supports Mixed-Mode Signal Operation on All – Level Translation Data I/O Ports – PCI Interface – 5-V Input Down to 3.3-V Output Level Shift – USB Interface With 3.3-V VCC – Memory Interleaving – 5-V/3.3-V Input Down to 2.5-V Output Level – Bus Isolation Shift With 2.5-V VCC • 5-V Tolerant I/Os With Device Powered Up or 3 Description Powered Down The SN74CB3T3306 device is a high-speed TTL- • Bidirectional Data Flow With Near-Zero compatible FET bus switch with low ON-state resistance (ron), allowing for minimal propagation Propagation Delay delay. The device fully supports mixed-mode signal • Low ON-State Resistance (ron) Characteristics (ron operation on all data I/O ports by providing voltage = 5 Ω Typical) translation that tracks VCC. The SN74CB3T3306 • Low Input/Output Capacitance Minimizes Loading device supports systems using 5-V TTL, 3.3-V (Cio(OFF) = 4.5 pF Typical) LVTTL, and 2.5-V CMOS switching standards, as well as user-defined switching levels (see Figure 5). • Data and Control Inputs Provide Undershoot Clamp Diodes Device Information(1) • Low Power Consumption (ICC = 20 μA Maximum) PART NUMBER PACKAGE BODY SIZE (NOM) • VCC Operating Range From 2.3 V to 3.6 V SN74CB3T3306DCT SSOP (8) 2.95 mm × 2.80 mm • Data I/Os Support 0- to 5-V Signaling Levels (0.8 SN74CB3T3306DCU VSSOP (8) 2.30 mm × 2.00 mm V, 1.2 V, 1.5 V, 1.8 V, 2.5 V, 3.3 V, 5 V) (1) For all available packages, see the orderable addendum at • Control Inputs Can Be Driven by TTL or 5-V/3.3-V the end of the data sheet. CMOS Outputs • Ioff Supports Partial-Power-Down Mode Operation Block Diagram • Latch-Up Performance Exceeds 250 mA Per JESD 17 • ESD Performance Tested Per JESD 22 – 2000-V Human Body Model (A114-B, Class II) – 1000-V Charged-Device Model (C101) • Supports Digital Applications: – Level Translation – USB Interface – Bus Isolation • Ideal for Low-Power Portable Equipment 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. |
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