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TPS54227DRCR Fiches technique(PDF) 3 Page - Texas Instruments |
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TPS54227DRCR Fiches technique(HTML) 3 Page - Texas Instruments |
3 / 24 page TPS54227 (HSOP8) PowerPAD TM 1 2 3 4 8 7 6 5 SW GND VBST VIN EN VFB VREG5 SS EN VFB VREG5 SS GND VIN VIN VBST SW SW Exposed Thermal Die PAD on Underside PGND 1 2 3 4 5 10 9 8 7 6 TPS54227 www.ti.com SLVSAU2C – MAY 2011 – REVISED DECEMBER 2015 5 Pin Configuration and Functions DDA Package DRC Package 8-Pin HSOP 10-Pin VSON Top View Top View Pin Functions PIN I/O DESCRIPTION NAME DDA DRC EN 1 1 I Enable input control. EN is active high and must be pulled up to enable the device. Thermal pad of the package. Must be soldered to achieve appropriate dissipation. Must — Exposed be connected to GND. Thermal G Thermal pad of the package. PGND power ground return of internal low-side FET. Must Pad — be soldered to achieve appropriate dissipation. Ground pin. Power ground return for switching circuit. Connect sensitive SS and VFB GND 5 5 G returns to GND at a single point. SS 4 4 O Soft-start control. An external capacitor should be connected to GND. SW 6 6, 7 O Switch node connection between high-side NFET and low-side NFET. Supply input for the high-side FET gate drive circuit. Connect 0.1-µF capacitor between VBST 7 8 I VBST and SW pins. An internal diode is connected between VREG5 and VBST. VFB 2 2 I Converter feedback input. Connect to output voltage with feedback resistor divider. VIN 8 9, 10 P Input voltage supply pin. 5.5-V power supply output. A capacitor (typical 1 µF) should be connected to GND. VREG5 3 3 O VREG5 is not active when EN is low. Copyright © 2011–2015, Texas Instruments Incorporated Submit Documentation Feedback 3 Product Folder Links: TPS54227 |
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