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Moteur de recherche de fiches techniques de composants électroniques |
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Moteur de recherche de fiches techniques de composants électroniques |
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UC1875-SP Fiches technique(PDF) 7 Page - Texas Instruments |
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UC1875-SP Fiches technique(HTML) 7 Page - Texas Instruments |
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7 / 36 page  200 % T q = f (4) Phase shift percentage (0% = 0 , 100% = 180 ) is defined as where is the phase shift, and and T are defined in Figure 1. UC1875-SP www.ti.com SLUSAQ9B – DECEMBER 2011 – REVISED DECEMBER 2015 7.5 Electrical Characteristics –55°C < TA < 125°C. VC = VIN = 12 V, R(FREQSET) = 12 kΩ, C(FREQSET) = 330 pF, R(SLOPE) = 12 kΩ, C(RAMP) = 200 pF, C(DELAYSET A-B) = C(DELAYSET C-D) = 0.01 µF, I(DELAYSET A-B) = I(DELAYSET C-D) = –500 µA, TA = TJ, unless otherwises stated. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT UNDERVOLTAGE LOCKOUT Start threshold 10.75 11.75 V UVLO hysteresis 0.5 1.25 2 V SUPPLY CURRENT VIN = 8 V, VC = 20 V, R(SLOPE) open, IIN Startup 150 600 μA I(DELAY) = 0 VIN = 8 V, VC = 20 V, R(SLOPE) open, IC Startup 10 100 µA I(DELAY) = 0 IIN 30 44 mA IC 15 30 mA VOLTAGE REFERENCE Output voltage TJ = 25°C 4.92 5 5.08 V Line regulation 11 V < VIN < 20 V 1 10 mV Load regulation IVREF = –10 mA 5 20 mV Total variation Line, Load, Temperature 4.9 5.1 V Noise Voltage 10 Hz to 10 kHz 50 µVrms Long Term Stability TJ = 125°C, 1000 hours 2.5 mV Short circuit current VREF = 0 V, TJ = 25°C 60 mA ERROR AMPLIFIER Offset voltage 5 15 mV Input bias current 0.6 3 μA AVOL 1 V < V(E/AOUT) < 4 V 60 90 dB CMMR 1.5 V < VCM < 5.5 V 75 95 dB PSRR 11 V < VIN < 20 V 85 100 dB Output sink current V(E/AOUT) = 1 V 1 2.5 mA Output source current I(E/AOUT) = 4 V –1.3 –0.5 mA Output voltage high I (E/AOUT) = –0.5 mA 4 4.7 5 V Output voltage low I(E/AOUT) = 1 mA 0 0.5 1 V 01 device 5 Unity Gain BW See (1) MHz 02 device 7 Slew rate See (1) 6 11 V/ μs PWM COMPARATOR RAMP offset voltage TJ = 25°C (2) 1.3 V Zero phase shift voltage See (3) 0.55 0.9 V 01 device 98% 99.5% 102% V(E/AOUT) > (Ramp Peak + Ramp Offset) PWM phase shift (4)(5) 02 device 96% 100% 104% V(E/AOUT) < Zero Phase Shift Voltage 0% 0.5% 2% Output skew (4) (5) V(E/AOUT) > 1 V 5 ±20 ns Ramp to output delay (6) (1) 65 125 (1) Not production tested. (2) Ramp offset voltage has a temperature coefficient of about –4 mV/°C. (3) The zero phase shift voltage has a temperature coefficient of about –2 mV/°C. At 0% phase shift, is the output skew. (5) Not production tested at –55·C. (6) Ramp delay to output time is defined in Figure 1 Copyright © 2011–2015, Texas Instruments Incorporated Submit Documentation Feedback 7 Product Folder Links: UC1875-SP |
Numéro de pièce similaire - UC1875-SP_15 |
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Description similaire - UC1875-SP_15 |
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