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SN74TVC3306 Fiches technique(PDF) 9 Page - Texas Instruments |
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SN74TVC3306 Fiches technique(HTML) 9 Page - Texas Instruments |
9 / 19 page 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 ±1 0 1 2 3 4 V IN (V) -40°C 25°C 85°C C001 SN74TVC3306 www.ti.com SCDS112D – MARCH 2001 – REVISED DECEMBER 2014 Typical Application (continued) 10.2.1 Design Requirements 10.2.1.1 Application Operating Conditions Application Operating Conditions (See Figure 3) MIN TYP(1) MAX UNIT VBIAS BIAS voltage VREF + 0.6 2.1 5 V VGATE GATE voltage VREF + 0.6 2.1 5 V VREF Reference voltage 0 1.5 4.4 V VDPU Drain pullup voltage 2.36 2.5 2.64 V IPASS Pass-transistor current 14 mA IREF Reference-transistor current 5 μA TA Operating free-air temperature –40 85 °C (1) All typical values are at TA = 25°C. 10.2.2 Detailed Design Procedure For the clamping configuration, the common GATE input must be connected to one side (An or Bn) of any one of the pass transistors, making that the VBIAS connection of the reference transistor and the opposite side (Bn or An) the VREF connection. When VBIAS is connected through a 200-kΩ resistor to a 3-V to 5.5-V VCC supply and VREF is set to 0 V to VCC – 0.6 V, the output of each switch has a maximum clamp voltage equal to VREF. A filter capacitor on VBIAS is recommended. 10.2.3 Application Curves Figure 4. On-resistance vs VIN (A to B, 15 mA current) Copyright © 2001–2014, Texas Instruments Incorporated Submit Documentation Feedback 9 Product Folder Links: SN74TVC3306 |
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