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S3C4530A Datasheet(Fiches technique) 30 Page - Samsung semiconductor

Numéro de pièce S3C4530A
Description  16/32-bit RISC microcontroller is a cost-effective, high-performance microcontroller
Télécharger  432 Pages
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Fabricant  SAMSUNG [Samsung semiconductor]
Site Internet  http://www.samsung.com/Products/Semiconductor
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S3C4530A Datasheet(HTML) 30 Page - Samsung semiconductor

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PROGRAMMER'S MODEL
S3C4530A
2-4
REGISTERS
ARM7TDMI has a total of 37 registers-31 general-purpose 32-bit registers and six status registers - but these
cannot all be seen at once. The processor state and operating mode dictate which registers are available to the
programmer.
The ARM State Register Set
In ARM state, 16 general registers and one or two status registers are visible at any one time. In privileged (non-
User) modes, mode-specific banked registers are switched in. Figure 2-3 shows which registers are available in
each mode: the banked registers are marked with a shaded triangle.
The ARM state register set contains 16 directly accessible registers: R0 to R15. All of these except R15 are
general-purpose, and may be used to hold either data or address values. In addition to these, there is a
seventeenth register used to store status information.
Register 14
is used as the subroutine link register. This receives a copy of R15 when a branch
and link (BL) instruction is executed. At all other times it may be treated as a
general-purpose register. The corresponding banked registers R14_svc, R14_irq,
R14_fiq, R14_abt and
R14_und are similarly used to hold the return values of
R15 when interrupts and exceptions arise, or when branch and link instructions are
executed within interrupt or exception routines.
Register 15
holds the Program Counter (PC). In ARM state, bits [1:0] of R15 are zero and bits
[31:2] contain the PC. In THUMB state, bit [0] is zero and bits [31:1] contain the PC.
Register 16
is the CPSR (Current Program Status Register). This contains condition code flags
and the current mode bits.
FIQ mode has seven banked registers mapped to R8-14 (R8_fiq-R14_fiq). In ARM state, many FIQ handlers do
not need to save any registers. User, IRQ, Supervisor, Abort and Undefined each have two banked registers
mapped to R13 and R14, allowing each of these modes to have a private stack pointer and link registers.


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