Moteur de recherche de fiches techniques de composants électroniques
Selected language     French  ▼

Delete All
ON OFF
ALLDATASHEET.FR

X  

Preview PDF Download HTML

S3C4530A Datasheet(Fiches technique) 21 Page - Samsung semiconductor

Numéro de pièce S3C4530A
Description  16/32-bit RISC microcontroller is a cost-effective, high-performance microcontroller
Télécharger  432 Pages
Scroll/Zoom Zoom In 100% Zoom Out
Fabricant  SAMSUNG [Samsung semiconductor]
Site Internet  http://www.samsung.com/Products/Semiconductor
Logo 

S3C4530A Datasheet(HTML) 21 Page - Samsung semiconductor

Zoom Inzoom in Zoom Outzoom out
 21 / 432 page
background image
S3C4530A
PRODUCT OVERVIEW
1-21
REGISTERS
The S3C4530A CPU core has a total of 37 registers: 31 general-purpose 32-bit registers, and 6 status registers.
Not all of these registers are always available. Whether a registers is available to the programmer at any given
time depends on the current processor operating state and mode.
NOTE
When the S3C4530A is operating in ARM state, 16 general registers and one or two status registers can
be accessed at any time. In privileged mode, mode-specific banked registers are switched in.
Two register sets, or banks, can also be accessed, depending on the core
′s current state, the ARM state register
set and the THUMB state register set:
The ARM state register set contains 16 directly accessible registers: R0-R15. All of these registers, except for
R15, are for general-purpose use, and can hold either data or address values. An additional (17th) register,
the CPSR (Current Program Status Register), is used to store status information.
The THUMB state register set is a subset of the ARM state set. You can access 8 general registers, R0-R7,
as well as the program counter (PC), a stack pointer register (SP), a link register (LR), and the CPSR. Each
privileged mode has a corresponding banked stack pointer, link register, and saved process status register
(SPSR).
The THUMB state registers are related to the ARM state registers as follows:
THUMB state R0-R7 registers and ARM state R0-R7 registers are identical
THUMB state CPSR and SPSRs and ARM state CPSR and SPSRs are identical
THUMB state SP, LR, and PC are mapped directly to ARM state registers R13, R14, and R15, respectively
In THUMB state, registers R8-R15 are not part of the standard register set. However, you can access them for
assembly language programming and use them for fast temporary storage, if necessary.


Html Pages

1  2  3  4  5  6  7  8  9  10  11  12  13  14  15  16  17  18  19  20  21  22  23  24  25  26  27  28  29  30  31  32  33  34  35  36  37  38  39  40  41  42  43  44  45  46  47  48  49  50  51  52  53  54  55  56  57  58  59  60  61  62  63  64  65  66  67  68  69  70  71  72  73  74  75  76  77  78  79  80  81  82  83  84  85  86  87  88  89  90  91  92  93  94  95  96  97  98  99  100   ...More


Datasheet Download




Lien URL



Privacy Policy
ALLDATASHEET.FR
AllDATASHEET vous a-t-il été utile ?   [ DONATE ]  

À propos de Alldatasheet   |   Publicit   |   Contactez-nous   |   Politique de confidentialit   |   Echange de liens   |   Manufacturer List
All Rights Reserved© Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn