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FM1608-120 Fiches technique(PDF) 2 Page - Ramtron International Corporation |
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FM1608-120 Fiches technique(HTML) 2 Page - Ramtron International Corporation |
2 / 12 page Ramtron FM1608 28 July 2000 2/12 Figure 1. Block Diagram Pin Description Pin Name Pin Number I/O Pin Description A0-A12 2-10, 21, 23-25 I Address. The 13 address lines select one of 8,192 bytes in the FRAM array. The address value will be latched on the falling edge of /CE. DQ0-7 11-13, 15-19 I/O Data. 8-bit bi-directional data bus for accessing the FRAM array. /CE 20 I Chip Enable. /CE selects the device when low. The falling edge of /CE causes the address to be latched internally. Address changes that occur after /CE goes low will be ignored until the next falling edge occurs. /OE 22 I Output Enable. When /OE is low the FM1608 drives the data bus when valid data is available. Taking /OE high causes the DQ pins to be tri- stated. /WE 27 I Write Enable. Taking /WE low causes the FM1608 to write the contents of the data bus to the address location latched by the falling edge of /CE. VDD 28 I Supply Voltage. 5V VSS 14 I Ground. Functional Truth Table /CE /WE /OE Function H X X Standby/Precharge æ X X Latch Address L H L Read L L X Write Address Latch A0-A12 CE Control Logic WE Row Decoder Block Decoder Column Decoder 1Kx8 A0-A7 A8-A9 A10-A12 I/O Latch Bus Driver OE DQ0-7 1Kx8 1Kx8 1Kx8 1Kx8 1Kx8 1Kx8 1Kx8 |
Numéro de pièce similaire - FM1608-120 |
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Description similaire - FM1608-120 |
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