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VNH7100ASTR Fiches technique(PDF) 11 Page - STMicroelectronics |
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VNH7100ASTR Fiches technique(HTML) 11 Page - STMicroelectronics |
11 / 38 page DocID028092 Rev 4 11/38 VNH7100AS Electrical specifications 37 Table 9. Protections and diagnostics (VCC = 7 V up to 18 V; -40°C < Tj < 150°C) Symbol Parameter Test conditions Min. Typ. Max. Unit VUSD Undervoltage shutdown 4 V VUSDreset Undervoltage shutdown reset 5V VUSDHyst Undervolatge shutdown Hysteresis 0.4 V ILIM_H High-side current limitation 12 18 24 A ISD_LS Shutdown LS current 14 22 30 A tSD_LS Time to shutdown for the low-side VINA =VINB =0 V; PWM = 5 V (see Figure 8) 5µs VCL_HSD High-side clamp voltage (VCC to OUTA =0 or OUTB =0) IOUT = 100 mA; tCLAMP =1 ms 38 46 V VCL_LSD Low-side clamp voltage (OUTA =VCC or OUTB = VCC to GND) IOUT = 100 mA; tCLAMP =1 ms 38 46 V TTSD_HS High-side thermal shutdown temperature INx = 2.1 V 150 175 200 °C TTR_HS High-side thermal reset temperature 135 °C THYST_HS High-side thermal hysteresis (TSD_HS - TR_HS) 7°C TTSD_LS Low-side thermal shutdown temperature INx = 0 V 150 175 200 °C VCL Total clamp voltage (VCC to GND) IOUT = 100 mA; tCLAMP =1 ms 38 46 52 V VOL OFF-state open-load voltage detection threshold INA =INB = 0; PWM = 0; VSEL0 = 5 V for CHA; VSEL0 = 0 V and within tD_STBY for CHB 23 4 V IL(off2) OFF-state output sink current INA =INB =0; VOUTx =VOL; PWM = 0 V; VSEL0 =5 V for CHA; VSEL0 = 0 V and within tD_STBY for CHB -100 -15 µA tDSTKON OFF-state diagnostic delay time from falling edge of INPUT (see Figure 4) INA = 5 V to 0 V; INB =0 V; VSEL0 =5 V; IOUT = 0 A; VOUTA =4 V; PWM= 0V 40 150 350 µs tD_VOL (1) OFF-state diagnostic delay time from rising edge of VOUT (see Figure 11) INA =INB = 0 V; PWM = 0 V; VOUTx = 0 V to 4 V; VSEL0 = 5 V for CHA; VSEL0 = 0 V and within tD_STBY for CHB 530 µs |
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