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TD351ID Fiches technique(PDF) 8 Page - STMicroelectronics |
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TD351ID Fiches technique(HTML) 8 Page - STMicroelectronics |
8 / 19 page Functional description TD351 8/19 Doc ID 10977 Rev 2 5 Functional description 5.1 Input stage The TD351 input is compatible with optocouplers or pulse transformers. The input is triggered by the signal edge and allows the use of low-sized, low-cost pulse transformers. Input is active low and output is driven high when input is driven low. The IN input is internally clamped at about 5 V to 7 V. When using an open collector optocoupler, the resistive pull-up resistor can be connected to either VREF or VH. Recommended pull-up resistor value with VH = 16 V is from 4.7 k Ω to 22 kΩ. When driven by a pulse transformer, the input positive and negative pulse widths at the Vton and Vtoff threshold voltages must be larger than the minimum pulse width tonmin (see Figure 6). This feature acts as a filter against invalid input pulses smaller than tonmin. 5.2 Voltage reference A voltage reference is used to create accurate timing for the turn-on delay with external resistor and capacitor. The same circuitry is also used for the two-level turn-off delay. A decoupling capacitor (10 nF to 100 nF) on the VREF pin is required to ensure good noise rejection. 5.3 Active Miller clamp The TD351 offers an alternative solution to the problem of Miller current in IGBT switching applications. Instead of driving the IGBT gate to a negative voltage to increase the safety margin, the TD351 uses a dedicated CLAMP pin to control the Miller current. When the IGBT is off, a low impedance path is established between the IGBT gate and emitter to carry the Miller current, and the voltage spike on the IGBT gate is greatly reduced. During turn-off, the gate voltage is monitored and the clamp output is activated when the gate voltage goes below 2 V (relative to VL). The clamp voltage is VL+4V max for a Miller current up to 500 mA. The clamp is disabled when the IN input is triggered again. The CLAMP function does not affect the turn-off characteristic, but only keeps the gate at low level throughout the OFF-time. The main benefit is that negative voltage can be avoided in many cases, allowing a bootstrap technique for the high side driver supply. 5.4 Two-level turn-off During turn-off, the gate voltage can be reduced to a programmable level in order to reduce the IGBT current (in the event of overcurrent). This action prevents both dangerous overvoltages across the IGBT and RBSOA problems, especially at short-circuit turn-off. The turn-off (Ta) delay is programmable through external resistor Rd and capacitor Cd for accurate timing. |
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Description similaire - TD351ID |
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