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74F109SC Fiches technique(PDF) 2 Page - National Semiconductor (TI) |
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74F109SC Fiches technique(HTML) 2 Page - National Semiconductor (TI) |
2 / 10 page Connection Diagrams Unit Loading/Fan Out See Section 0 for U.L. definitions 54F/74F Pin Names Description U.L. Input I IH/IIL HIGH/LOW Output I OH/IOL J 1,J2,K1,K2 Data Inputs 1.0/1.0 20 µA/−0.6 mA CP 1,CP2 Clock Pulse Inputs (Active Rising Edge) 1.0/1.0 20 µA/−0.6 mA C D1,CD2 Direct Clear Inputs (Active LOW) 1.0/3.0 20 µA/−1.8 mA S D1,SD2 Direct Set Inputs (Active LOW) 1.0/3.0 20 µA/−1.8 mA Q 1,Q2,Q1,Q2 Outputs 50/33.3 −1 mA/20 mA Truth Table Inputs Outputs S D C D CP J K QQ LH X X X H L HL X X X L H LL X X X H H HH N ll L H HH N h l Toggle HH N lh Q 0 Q 0 HH N hh H L HH L X X Q 0 Q 0 H (h) = HIGH Voltage Level L (l) = LOW Voltage Level N = LOW-to-HIGH Transition X = Immaterial Q0 (Q0) = Before LOW-to-HIGH Transition of Clock Lower case letters indicate the state of the referenced output one setup time prior to the LOW-to-HIGH clock transition. Pin Assignment for DIP, SOIC and Flatpak DS009471-1 Pin Assignment for LCC DS009471-2 PrintDate=1997/08/28 PrintTime=11:45:23 10182 ds009471 Rev. No. 1 cmserv Proof 2 DSXXX www.national.com 2 |
Numéro de pièce similaire - 74F109SC |
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Description similaire - 74F109SC |
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