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Moteur de recherche de fiches techniques de composants électroniques |
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Moteur de recherche de fiches techniques de composants électroniques |
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TCAN1042VDRQ1 Fiches technique(PDF) 9 Page - Texas Instruments |
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TCAN1042VDRQ1 Fiches technique(HTML) 9 Page - Texas Instruments |
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9 / 32 page  9 TCAN1042-Q1, TCAN1042V-Q1, TCAN1042H-Q1 TCAN1042HV-Q1, TCAN1042G-Q1, TCAN1042GV-Q1 TCAN1042HG-Q1, TCAN1042HGV-Q1 www.ti.com SLLSES9 – FEBRUARY 2016 Product Folder Links: TCAN1042-Q1 TCAN1042V-Q1 TCAN1042H-Q1 TCAN1042HV-Q1 TCAN1042G-Q1 TCAN1042GV-Q1 TCAN1042HG-Q1 TCAN1042HGV-Q1 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated (1) All typical values are at 25°C and supply voltages of VCC = 5 V and VIO = 5 V, RL = 60 Ω. (2) The TXD dominant timeout (t(TXD_DTO)) disables the driver of the transceiver once the TXD has been dominant longer than t(TXD_DTO), which releases the bus lines to recessive, preventing a local failure from locking the bus dominant. The driver may only transmit dominant again after TXD has been returned HIGH (recessive). While this protects the bus from local faults, locking the bus dominant, it limits the minimum data rate possible. The CAN protocol allows a maximum of eleven successive dominant bits (on TXD) for the worst case, where five successive dominant bits are followed immediately by an error frame. This, along with the t(TXD_DTO) minimum, limits the minimum bit rate. The minimum bit rate may be calculated by: Minimum Bit Rate = 11 / t(TXD_DTO) 7.6 Switching Characteristics Over recommended operating conditions with TA = -55°C to 125°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT DEVICE SWITCHING CHARACTERISTICS tPROP(LOOP1) Total loop delay, driver input (TXD) to receiver output (RXD), recessive to dominant See Figure 8, STB = 0 V, RL = 60 Ω, CL = 100 pF, CL(RXD) = 15 pF 100 160 ns tPROP(LOOP2) Total loop delay, driver input (TXD) to receiver output (RXD), dominant to recessive 110 175 tMODE Mode change time, from Normal to Standby or from Standby to Normal See Figure 7 1 45 µs tWK_FILTER 0.5 1.85 DRIVER SWITCHING CHARACTERISTICS tpHR Propagation delay time, HIGH TXD to Driver Recessive See Figure 5, STB = 0 V, RL = 60 Ω, CL = 100 pF, RCM = open 75 ns tpLD Propagation delay time, LOW TXD to Driver Dominant 55 tsk(p) Pulse skew (|tpHR - tpLD|) 20 tR Differential output signal rise time 45 tF Differential output signal fall time 45 tTXD_DTO Dominant timeout(2) See Figure 10, STB = 0 V, RL = 60 Ω, CL = open 1.2 3.8 ms RECEIVER SWITCHING CHARACTERISTICS tpRH Propagation delay time, bus recessive input to high output See Figure 6, STB = 0 V, CL(RXD) = 15 pF 65 ns tpDL Propagation delay time, bus dominant input to low output 50 ns tR RXD Output signal rise time 10 ns tF RXD Output signal fall time 10 ns FD Timing Parameters tBIT(BUS) Bit time on CAN bus output pins with tBIT(TXD) = 500 ns, all devices See Figure 9 , STB = 0 V, RL = 60 Ω, CL = 100pF, CL(RXD) = 15pF 435 530 ns Bit time on CAN bus output pins with tBIT(TXD) = 200 ns, G device variants only 155 210 tBIT(RXD) Bit time on RXD output pins with tBIT(TXD) = 500 ns, all devices 400 550 Bit time on RXD output pins with tBIT(TXD) = 200 ns, G device variants only 120 220 ΔtREC Receiver timing symmetry with tBIT(TXD) = 500 ns, all devices -65 40 Receiver timing symmetry with tBIT(TXD) = 200 ns, G device variants only -45 15 |
Numéro de pièce similaire - TCAN1042VDRQ1 |
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Description similaire - TCAN1042VDRQ1 |
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