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Moteur de recherche de fiches techniques de composants électroniques |
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Moteur de recherche de fiches techniques de composants électroniques |
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DLPC6401ZFF Fiches technique(PDF) 9 Page - Texas Instruments |
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DLPC6401ZFF Fiches technique(HTML) 9 Page - Texas Instruments |
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9 / 50 page  DLPC6401 www.ti.com DLPS031C – DECEMBER 2013 – REVISED AUGUST 2015 Pin Functions (continued) PIN(1) I/O (2) INTERNAL TERMINATION CLK SYSTEM DESCRIPTION NAME NO. POWER TYPE PERIPHERAL INTERFACE UART_TXD L19 VDD33 O2 Async Transmit data output. Reserved for debug messages UART_RXD L21 VDD33 I4 Async Receive data input. Reserved for debug messages Ready to send hardware flow control output. UART_RTS M19 VDD33 O2 Async Reserved for debug messages Clear to send hardware flow control input. Reserved UART_CTS L20 VDD33 I4 Async for debug messages GENERAL PURPOSE I/O (GPIO) (7) GPIO_37 K21 VDD33 B2 Async None GPIO_36 G1 VDD33 B2 Async None GPIO_35 H4 VDD33 B2 Async None GPIO_34 H3 VDD33 B2 Async None GPIO_33 H2 VDD33 B2 Async None GPIO_32 F22 VDD33 B2 Async None GPIO_31 G19 VDD33 B2 Async None GPIO_29 F20 VDD33 B2 Async None GPIO_28 E22 VDD33 B2 Async None GPIO_27 E21 VDD33 B2 Async None GPIO_25 D22 VDD33 B2 Async None GPIO_24 E20 VDD33 B2 Async None GPIO_23 D21 VDD33 B2 Async None GPIO_21 N20 VDD33 B2 Async None GPIO_20 N19 VDD33 B2 Async None GPIO_19 D18 VDD33 B2 Async None GPIO_18 C18 VDD33 B2 Async None GPIO_15 B19 VDD33 B2 Async None GPIO_14 B18 VDD33 B2 Async None GPIO_13 L2 VDD33 B2 Async None GPIO_12 M4 VDD33 B2 Async None GPIO_11 A19 VDD33 B2 Async None GPIO_10 C17 VDD33 B2 Async None GPIO_06 A18 VDD33 B2 Async None GPIO_05 D16 VDD33 B2 Async None GPIO_04 C16 VDD33 B2 Async None GPIO_03 B16 VDD33 B2 Async None GPIO_02 A17 VDD33 B2 Async None GPIO_00 C15 VDD33 B2 Async None OTHER INTERFACES Feedback from fan to indicate fan is connected and FAN_LOCKED B17 VDD33 B2 Async running FAN_PWM D15 VDD33 B2 Async Fan PWM speed control BOARD LEVEL TEST AND DEBUG TDI P18 VDD33 I4 Includes internal pullup TCK JTAG serial data in(8) TCK R18 VDD33 I4 Includes internal pullup N/A JTAG serial data clock(8) TMS1 V15 VDD33 I4 Includes internal pullup TCK JTAG test mode select(8) TDO1 L18 VDD33 O1 TCK JTAG serial data out(8) (7) GPIO signals must be configured by software for input, output, bidirectional, or open-drain. Some GPIOs have one or more alternate use modes, which are also software configurable. The reset default for all optional GPIOs is as an input signal. However, any alternate function connected to these GPIO pins with the exception of general-purpose clocks and PWM generation, are reset. An external pullup to the 3.3-V supply is required for each signal configured as open-drain. External pullup or pulldown resistors may be required to ensure stable operation before software is able to configure these ports. (8) All JTAG signals are LVCMOS-compatible. Copyright © 2013–2015, Texas Instruments Incorporated Submit Documentation Feedback 9 Product Folder Links: DLPC6401 |
Numéro de pièce similaire - DLPC6401ZFF |
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Description similaire - DLPC6401ZFF |
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