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TS1110-200ITQ1633 Datasheet(Fiches technique) 5 Page - Silicon Laboratories

Numéro de pièce TS1110-200ITQ1633
Description  Power Management Systems
Télécharger  22 Pages
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TS1110-200ITQ1633 Datasheet(HTML) 5 Page - Silicon Laboratories

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2.3 Sign Output
The TS1107/10 SIGN output indicates the load current’s direction. The SIGN output is a logic HIGH when M1 is conducting current
(VRS+ > VRS–). Alternatively, the SIGN output is a logic LOW when M2 is conducting current (VRS– > VRS+). The SIGN comparator’s
transfer characteristic is illustrated in Figure 1. Unlike other current-sense amplifiers that implement an OUT/SIGN arrangement, the
TS1107/10 exhibits no “dead zone” at ILOAD switchover.
Figure 2.3. TS1107/10 Sign Output Transfer Characteristic
2.4 Current Limit Comparator
The TS1107/10 provides a comparator which can be used for current limit detection. The current limit threshold can be set to detect
either positive or negative current, though it provides fastest response in the positive direction. In a typical configuration, the inverting
terminal, CIN– is connected to OUT. The non-inverting terminal of the comparator, CIN+, should be supplied with an external voltage or
a resistor divider from the supply voltage, which is used as the threshold voltage for the current limiter. The output of the comparator is
latch capable only when the Sign Comparator is HIGH (VRS+>VRS–), and CLATCH is held HIGH. Once the comparator output (COUT)
is triggered, COUT will latch HIGH and maintain the HIGH state as long as CLATCH is held HIGH. To reset COUT to the default com-
parator output state, CLATCH must be held or strobed LOW.
2.5 FET Control (TS1110 Only)
A “circuit breaker” feature is supplied within the TS1110 as a FET control which drives the gate drive of an external P-channel MOS-
FET. When the Current Limit Comparator’s output goes HIGH and the LATCH feature is enabled, the FET control output will latch HIGH
thereby disconnecting current flow to the load by holding the gate of the external PMOS HIGH. To resume current flow to the load, the
FET control must be brought low by holding or strobing CLATCH low. The output of the comparator controls the gate logic of an internal
FET whereby the source is connected to the non-inverting terminal of the CSA, RS+, while the drain is fed to the FET pin. The FET pin
is intended to drive the gate of an external PMOS, where the PMOS source is connected to the inverting terminal of the CSA, RS–, and
the drain is connected to the external load. FET will maintain its logic LOW state while the comparator output, COUT, is LOW. When
COUT is latched HIGH, the FET pin will latch to a HIGH state, thereby switching and holding the external PMOS OFF. The FET control
features a Turn ON Time, tFET(ON), of 720 ns(typ) and a Turn OFF Time, tFET(OFF), of 2.9 ms(typ) when driving a 860 pF gate capaci-
tance. Note that the FET Control is a pull-up only. A pull-down resistor is required from the external FET’s gate to ground to ensure the
FET is normally ON.
2.6 VREF Divider
The TS1107/10 provides an internal voltage divider network to set VBIAS, eliminating the need for externally setting the voltage. The
VREF Divider is activated once the voltage applied to VREF is 0.9 V or greater. The VREF divider connects to VBIAS, where the VBIAS
voltage is equal to 50% of VREF . The VREF Divider exhibits a total series resistance of 9.2 MΩ from VREF to GND.
TS1107/10 Data Sheet
System Overview | Smart. Connected. Energy-friendly.
Rev. 1.0 | 4

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