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DLPC300 Fiches technique(PDF) 5 Page - Texas Instruments |
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DLPC300 Fiches technique(HTML) 5 Page - Texas Instruments |
5 / 51 page DLPC300 www.ti.com DLPS023C – JANUARY 2012 – REVISED AUGUST 2015 Pin Functions (continued) PIN I/O I/O CLK SYSTEM DESCRIPTION POWER TYPE NAME NO. CONTROL I2C clock. Bidirectional, open-drain signal. An external pullup is required. No I2C activity is permitted for a SCL A10 VCC_ INTF B38 N/A minimum of 100 ms after PARK and RESET are set high. I2C data. Bidirectional, open-drain signal. An external SDA C10 VCC_ INTF B38 SCL pullup is required. Primary usage is to indicate when auto-initialization is complete, which is when INIT_DONE transitions high INIT_DONE C9 VCC_ INTF B34 Async then low following release of RESET. INIT_DONE also helps flag a detected error condition in the form of a logic-high, pulsed interrupt flag. PARALLEL RGB INTERFACE PARALLEL RGB MODE BT.656 I/F MODE PCLK D13 VCC_ INTF I3 N/A Pixel clock(2) Pixel clock(2) Not used, pulldown through Not used, pulldown through an PDM H15 VCC_ INTF B34 ASYNC an external resistor. external resistor. VSYNC H14 VCC_ INTF I3 ASYNC VSync(3) Unused(4) HSYNC H13 VCC_ INTF I3 PCLK HSync(3) Unused(4) DATEN G15 VCC_ INTF I3 PCLK Data valid(2) Unused(4) PDATA[0] G14 VCC_ INTF I3 PCLK Data0(5) Data0(5) PDATA[1] G13 VCC_ INTF I3 PCLK Data1(5) Data1(5) PDATA[2] F15 VCC_ INTF I3 PCLK Data2(5) Data2(5) PDATA[3] F14 VCC_ INTF I3 PCLK Data3(5) Data3(5) PDATA[4] F13 VCC_ INTF I3 PCLK Data4(5) Data4(5) PDATA[5] E15 VCC_ INTF I3 PCLK Data5(5) Data5(5) PDATA[6] E14 VCC_ INTF I3 PCLK Data6(5) Data6(5) PDATA[7] E13 VCC_ INTF I3 PCLK Data7(5) Data7(5) PDATA[8] D15 VCC_ INTF I3 PCLK Data8(5) Unused(4) PDATA[9] D14 VCC_ INTF I3 PCLK Data9(5) Unused(4) PDATA[10] C15 VCC_ INTF I3 PCLK Data10(5) Unused(4) PDATA[11] C14 VCC_ INTF I3 PCLK Data11(5) Unused(4) PDATA[12] C13 VCC_ INTF I3 PCLK Data12(5) Unused(4) PDATA[13] B15 VCC_ INTF I3 PCLK Data13(5) Unused(4) PDATA[14] B14 VCC_ INTF I3 PCLK Data14(5) Unused(4) PDATA[15] A15 VCC_ INTF I3 PCLK Data15(5) Unused(4) PDATA[16] A14 VCC_ INTF I3 PCLK Data16(5) Unused(4) PDATA[17] B13 VCC_ INTF I3 PCLK Data17(5) Unused(4) PDATA[18] A13 VCC_ INTF I3 PCLK Data18(5) Unused(4) PDATA[19] C12 VCC_ INTF I3 PCLK Data19(5) Unused(4) PDATA[20] B12 VCC_ INTF I3 PCLK Data20(5) Unused(4) PDATA[21] A12 VCC_ INTF I3 PCLK Data21(5) Unused(4) PDATA[22] C11 VCC_ INTF I3 PCLK Data22(5) Unused(4) PDATA[23] B11 VCC_ INTF I3 PCLK Data23(5) Unused(4) (2) Pixel clock capture edge is software programmable. (3) VSYNC, HSYNC and data valid polarity is software programmable. (4) Unused inputs should be pulled down to ground through an external resistor. (5) PDATA[23:0] bus mapping is pixel-format and source-mode dependent. See later sections for details. Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback 5 Product Folder Links: DLPC300 |
Numéro de pièce similaire - DLPC300_15 |
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Description similaire - DLPC300_15 |
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