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Moteur de recherche de fiches techniques de composants électroniques |
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Moteur de recherche de fiches techniques de composants électroniques |
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DLP5500BFYA Fiches technique(PDF) 11 Page - Texas Instruments |
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DLP5500BFYA Fiches technique(HTML) 11 Page - Texas Instruments |
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11 / 46 page  50% 50% tc fclock = 1 / tc SCPCLK SCPDI 50% tSCP_SKEW SCPD0 50% tSCP_DELAY DLP5500 www.ti.com DLPS013F – APRIL 2010 – REVISED MAY 2015 8.7 Timing Requirements over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT LVDS TIMING PARAMETERS (See Figure 9) tc Clock Cycle DLCK_A or DCLKC_B 5 ns tw Pulse Width DCLK_A or DCLK_B 2.5 ns ts Setup Time, D_A[0:15] before DCLK_A .35 ns ts Setup Time, D_B[0:15] before DCLK_B .35 ns th Hold Time, D_A[0:15] after DCLK_A .35 ns th Hold Time, D_B[0:15] after DCLK_B .35 ns tskew Channel B relative to Channel A –1.25 1.25 ns LVDS WAVEFORM REQUIREMENTS (See Figure 6) |VID| Input Differential Voltage (absolute difference) 100 400 600 mV VCM Common Mode Voltage 1200 mV VLVDS LVDS Voltage 0 2000 mV tr Rise Time (20% to 80%) 100 400 ps tr Fall Time (80% to 20%) 100 400 ps SERIAL CONTROL BUS TIMING PARAMETERS (See Figure 3 and Figure 4) fSCP_CLK SCP Clock Frequency 50 500 kHz tSCP_SKEW Time between valid SCP_DI and rising edge of SCP_CLK –300 300 ns tSCP_DELAY Time between valid SCP_DO and rising edge of SCP_CLK 2600 ns Time between falling edge of SCP_EN and the first rising edge of tSCP_EN 30 ns SCP_CLK tr_SCP Rise time for SCP signals 200 ns tfP Fall time for SCP signals 200 ns Figure 3. Serial Communications Bus Timing Parameters Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback 11 Product Folder Links: DLP5500 |
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Description similaire - DLP5500BFYA |
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