AN400

4

Rev. 0.5

2. Si474x 4x4 mm QFN Schematic and Layout

This section describes the minimum schematic and layout options required for optimal Si474x performance.

Population options are provided to support layouts for different audio output options and mitigation of system noise.

2.1. Si474x 4x4 mm Design

C1 (22 nF) is a required bypass capacitor for VDD supply pin 13. Place C1 as close as possible to VDD pin 13 and

GND pin 14. Place a VIA connecting C1 VDD supply to the power rail such that the cap is closer to the Si474x than

the VIA. Route C1 GND directly and only to GND pin 14 with a wide, low-inductance trace. These

recommendations are made to reduce the size of the current loop created by the bypass cap and routing, minimize

bypass cap impedance, and return all currents to the GND pad.

C13 (22 nF), C17 (100 µF), and C19 (0.1 µF) are optional bypass capacitors for the VIO supply pin 12 and may be

placed to mitigate supply noise. Place C13, C17, and C19 as close as possible to the VIO pin 12 and the GND pin

14. Place VIAs connecting C13, C17, and C19 VIO supply to the power rail such that the capacitors are closer to

the Si474x than the VIAs. Route C13, C17, and C19 GND directly and only to GND pin 14 with wide, low-

inductance traces. These recommendations are made to reduce the size of the current loop created by the bypass

capacitors and routing, minimize bypass cap impedance, and return all currents to the GND pad.

C2 (2 pF) is a required shunt capacitor from the DFS pin to ground when using digital audio output (Si4741/43/45

only), and is used to prevent degradation of audio quality. Place the capacitor as close as possible to the DFS pin.

C6 (0.1 µF) and C18 (100 µF) are optional bypass capacitors to mitigate system noise in AM and FM frequencies.

Route them the same way as C1.

C8 and C9 (0.39 µF) are ac coupling capacitors for analog audio output from ROUT pin 15 and LOUT pin 16. The

input resistance of the amplifier and the capacitor will set the high-pass pole given by Equation 1. Placement

location is not critical.

Equation 1. High-Pass Pole Calculation

R12, R14, R26, R29, and R30 (25

to 2 k) are optional series termination resistors used to mitigate system

noise. The recommended value of the resistors is 2 k

 for optimal edge rate and noise suppression. Confirm that

timing requirements are met with the selected series termination resistor value. Place the series termination

resistors, R12, R14, R21, R24, R26, R29, and R30, as close to the host controller as possible.

R21 and R24 (25

 to 2 k) are optional series termination resistors used to mitigate system noise. The

recommended value of the resistors is 2 k

 for optimal edge rate and noise suppression. Confirm that timing

requirements are met with the selected series termination resistor value. Place the series termination resistors,

R21 and R24 as close to the chip input as possible.

R17 and R20 (22 k

) are optional pull-up resistors for the RSTB and SENB lines. The size of pull-up resistor value

will vary based on the number of devices, capacitance, and speed of the bus. Placement location is not critical.

R27 and R28 (22 k

) are optional pull-up resistors for the SCLK and SDIO lines required only when using an I2C

bus. The size of pull-up resistor value will vary based on the number of devices, capacitance, and speed of the bus.

Placement location is not critical. Refer to the I2C specification for additional design information.

R16 (25

to 2 k) is a required series termination resistor when using digital audio output (Si4741/43/45 only) and

is used to mitigate noise from the digital data routed from DOUT pin 17. The recommended value of the resistor is

604

 for optimal edge rate and noise suppression. Confirm that timing requirements are met with the selected

series termination resistor value. Place R16 as close to pin 17 as possible.

R15 (25

to 2 k) is a required series termination resistor when using digital audio (Si4741/43/45 only) and is

used to mitigate noise from the digital clock routed to GPO3/DCLK pin 19. The recommended value of the resistor

is 2 k

 for optimal edge rate and noise suppression. Confirm that timing requirements are met with the selected

series termination resistor value. Place R15 as close to the host controller as possible. Choosing a DCLK

frequency that is above the AM band reduces the chances of having DCLK harmonics that fall in the AM band and

create digital noise.

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1

2

RC

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