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SI4701 Fiches technique(PDF) 6 Page - Silicon Laboratories

No de pièce SI4701
Description  Device initialization sequence and busmode selection
Download  42 Pages
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Fabricant  SILABS [Silicon Laboratories]
Site Internet  http://www.silabs.com
Logo SILABS - Silicon Laboratories

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AN230
6
Rev. 0.9
2. Set the ENABLE bit high and the DISABLE bit high to place the device in powerdown mode. Note that all
register states are maintained so long as VIO is supplied and the RST pin is high.
3. Remove VA and VD supplies as needed.
To power up the device (after power down):
1. Si4703-C19 Errata Option 1: Perform a hard reset of the tuner by following steps 2, 3, and 4 of 2.1.1 Hardware
Initialization.
2. Note that VIO is still supplied in this scenario. If VIO is not supplied, refer to device initialization procedure above.
3. Supply VA and VD.
4. Set the ENABLE bit high and the DISABLE bit low to powerup the device.
Setting the RST pin low will disable analog and digital circuitry, reset the registers to their default settings, and
disable the bus. Setting the RST pin high will bring the device out of reset, place the device in powerdown mode,
and latch which bus mode will be used to communicate with the device. There are two methods for selecting the
bus mode. Method one uses the SEN and SDIO pins while method two uses GPIO1 and GPIO3 (See Figure 3).
Please refer to the data sheet for more information regarding bus selection and timing requirements of the RST
signal.
More details on the register access during powerup and powerdown can be found in Section "3.2.1.ENABLE
(02h.0)/DISABLE (02h.6)—Powerup Control" on page 11.
Figure 2. Powerup, Powerdown, and Reset State Diagram
<Process Name>
Powerdown
Read:
ENABLE = 0
DISABLE = 0
Inactive
Registers reset to
default values
Bus Inactive
Powerup
Read:
ENABLE = 1
DISABLE = 0
Partial
Powerdown
Read:
ENABLE = 0
DISABLE = X
RST = VIO
Write:
ENABLE = 1
DISABLE = 0
Write:
ENABLE = 0
DISABLE = X
Write:
ENABLE = 1
DISABLE = 0
Write:
ENABLE = 1
DISABLE = 1
RST = GND
VA Optional
VD Optional
VIO Optional
RCLK Optional
VIO must be supplied prior to the
rising edge of reset
VA Optional
VD Optional
VIO Required
RCLK Optional
VA, VD, and RCLK must be supplied
prior to writing ENABLE = 1
VA Required
VD Required
VIO Required
RCLK Required
Si4703-C19 Errata: Ensure RDSD
register is zero before enabling.
VA Optional
VD Optional
VIO Required
RCLK Optional
Device Status
Power Supply Status


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