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ADE7903ARWZ Fiches technique(PDF) 8 Page - Analog Devices |
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ADE7903ARWZ Fiches technique(HTML) 8 Page - Analog Devices |
8 / 20 page ADE7903 Data Sheet PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Figure 5. Pin Configuration Table 5. Pin Function Descriptions Pin No. Mnemonic Description 1, 19 VDD Supply Voltage. These pins provide the supply voltage for the ADE7903. Maintain the supply voltage at 3.3 V ± 10% for specified operation. Decouple each VDD pin to GND with a ceramic 100 nF capacitor and a single 10 µF capacitor in parallel. Connect the VDD pins externally. 2, 10, 11, 20 GND Ground Reference. Connect the GND pins externally. 3, 4, 5 V2P, V1P, VM Analog Inputs for the Voltage Channels. The voltage channels are used with the voltage transducers. V2P and V1P are pseudo differential voltage inputs with a maximum signal level of ±500 mV with respect to VM for specified operation. Use these pins with the related input circuitry, as shown in Figure 18. If V1P or V2P is not used, connect it to the VM pin. 6, 7 IM, IP Analog Inputs for the Current Channel. The current channel is used with shunts. IM and IP are pseudo differential voltage inputs with a maximum differential level of ±31.25 mV. Use these pins with the related input circuitry, as shown in Figure 18. 8 LDO 2.5 V Output of the Analog Low Dropout (LDO) Regulator. Decouple this pin with a 4.7 µF capacitor in parallel with a ceramic 100 nF capacitor to GND. Do not connect external load circuitry to this pin. 9 REF Voltage Reference. This pin provides access to the on-chip voltage reference. The on-chip reference has a nominal value of 1.2 V. Decouple this pin to GND with a 4.7 µF capacitor in parallel with a ceramic 100 nF capacitor. 12 CLKOUT/DREADY Clock Output (CLKOUT). When CLKOUT functionality is selected (see the Synchronizing Multiple ADE7912/ADE7913 and ADE7903 Devices section for details), the ADE7903 generates a digital signal synchronous to the master clock at the XTAL1 pin. Use CLKOUT to provide a clock to other ADE7912/ ADE7913 and ADE7903 devices on the board. Data Ready, Active Low (DREADY). When the DREADY functionality is selected (see the Synchronizing Multiple ADE7912/ADE7913 and ADE7903 Devices section for details), the ADE7903 generates an active low signal synchronous to the ADC output frequency. Use this signal to start reading the ADC outputs of the ADE7903. 13 XTAL1 Master Clock Input. An external clock can be provided at this logic input. The CLKOUT/DREADY signal of another appropriately configured ADE7903 (see the Synchronizing Multiple ADE7912/ADE7913 and ADE7903 Devices section for details) can be provided at this pin. Alternatively, a crystal with a maximum drive level of 0.5 mW and an equivalent series resistance (ESR) of 20 Ω can be connected across XTAL1 and XTAL2 to provide a clock source for the ADE7903. The clock frequency for specified operation is 4.096 MHz, but lower frequencies down to 3.6 MHz can be used. See the ADE7903 Clock section for more details. 14 XTAL2 Crystal, Second Input. A crystal with a maximum drive level of 0.5 mW and an ESR of 20 Ω can be connected across XTAL2 and XTAL1 to provide a clock source for the ADE7903. 15 MISO Data Output for SPI Port. Pull up this pin with a 10 kΩ resistor (see the ADE7903 Clock section for details). 16 MOSI Data Input for SPI Port. 17 SCLK Serial Clock Input for SPI Port. All serial data transfers are synchronized to this clock (see the ADE7903 Clock section). 18 CS Chip Select for SPI Port. ADE7903 TOP VIEW (Not to Scale) VDD 1 GND 2 V2P 3 V1P 4 GND 20 VDD 19 CS 18 SCLK 17 VM 5 MOSI 16 IM 6 MISO 15 IP 7 XTAL2 14 LDO 8 XTAL1 13 REF 9 CLKOUT/DREADY 12 GND 10 GND 11 Rev. 0 | Page 8 of 28 |
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