3.1.3 DSPLL Loop Bandwidth

The DSPLL loop bandwidth determines the amount of input clock jitter attenuation. Register configurable DSPLL loop bandwidth set-

tings in the range of 0.1 Hz to 100 Hz are available for selection. The DSPLL will always remain stable with less than 0.1 dB of peaking

regardless of the DSPLL loop bandwidth selection.

3.1.4 Fastlock Feature

Selecting a low DSPLL loop bandwidth (e.g., 1 Hz) will generally lengthen the lock acquisition time. The fastlock feature allows setting a

temporary fastlock loop bandwidth that is used during the lock acquisition process. Higher fastlock loop bandwidth settings will enable

the DSPLL to lock faster. Once lock acquisition has completed, the DSPLL’s loop bandwidth will automatically revert to the DSPLL

Loop Bandwidth setting. Fastlock loop bandwidth settings in the range of 100 Hz to 4 kHz are available for selection. The fastlock fea-

ture can be enabled or disabled by register configuration.

3.1.5 Modes of Operation

Once initialization is complete, the Si5380 operates in one of four modes: Free-run Mode, Lock Acquisition Mode, Locked Mode, or

Holdover Mode. A state diagram showing the modes of operation is shown in the figure below. The following sections describe each of

these modes in greater detail.

No valid

input clocks

selected

Lock Acquisition

(Fast Lock)

Locked

Mode

Holdover

Mode

Phase lock on

selected input

clock is achieved

Selected input

clock fails

An input is qualified

and available for

selection

Yes

Free-run

Valid input clock

selected

Reset and

Initialization

Power-Up

Is holdover

history valid?

No

Figure 3.2. Modes of Operation

3.1.6 Initialization and Reset

When power is applied, the device begins an initialization period where it downloads default register values and configuration data from

NVM and performs other initialization tasks. Communicating with the device through the serial interface is possible once this initializa-

tion period is complete. No clocks will be generated until the initialization is complete. There are two types of resets available. A hard

reset is functionally similar to a device power-up. All registers will be restored to the values stored in NVM and all circuits, including the

serial interface, will be restored to their initial state. A hard reset is initiated using the RSTb pin or by asserting the hard reset bit. A soft

reset bypasses the NVM download. It is simply used to initiate register configuration changes.

Si5380 Data Sheet

Functional Description

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