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SI5334 Fiches technique(PDF) 6 Page - Silicon Laboratories

No de pièce SI5334
Description  PIN-CONTROLLED ANY-FREQUENCY, ANY-OUTPUT QUAD CLOCK GENERATOR
Download  37 Pages
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Fabricant  SILABS [Silicon Laboratories]
Site Internet  http://www.silabs.com
Logo SILABS - Silicon Laboratories

SI5334 Fiches technique(HTML) 6 Page - Silicon Laboratories

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Si5334
6
Rev. 1.2
Spread Spectrum PP
Frequency Deviation
SSDEV
Clock frequency of 100 MHz4
—–0.5
%
Spread Spectrum Modulation
Rate
SSDEV
Clock frequency of 100 MHz
30
33
kHz
Table 4. Input and Output Clock Characteristics
(VDD = 1.8 V –5% to +10%, 2.5 V ±10%, or 3.3 V ±10%, TA = –40 to 85 °C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Units
Input Clock (AC Coupled Differential Input Clocks on Pins IN1/2, IN5/6)1
Frequency
fIN
5—
710
MHz
Differential Voltage
Swing
VPP
710 MHz input
0.4
2.4
VPP
Rise/Fall Time2
tR/tF
20%–80%
1.0
ns
Duty Cycle
DC
< 1 ns tr/tf
40
60
%
Input Impedance1
RIN
10
k
Input Capacitance
CIN
—3.5
pF
Input Clock (DC-coupled Single-Ended Input Clock on Pins IN3/4)
Frequency
fIN
CMOS
5
200
MHz
Input Voltage
VI
–0.1
3.73
VPP
Input Voltage Swing
200 MHz
0.8
VDD + 10%
VPP
Rise/Fall Time3
tR/tF
10%–90%
4
ns
Rise/Fall Time3
tR/tF
20%–80%
2.3
ns
Duty Cycle
DC
< 2 ns tr/tf
40
60
%
Input Capacitance
CIN
—2.0
pF
Output Clocks (Differential)
Notes:
1. Use an external 100
 resistor to provide load termination for a differential clock.
See "2.2. Crystal/Clock Input" on page 15.
2. For best jitter performance, keep the input slew rate on IN1/2, IN5/6 faster than 0.3 V/ns.
3. For best jitter performance, keep the input single ended slew rate on pins 3 or 4 faster than 1 V/ns.
4. Only two unique frequencies above Fvco/8 can be simultaneously output, Fvco/4 and Fvco/6.
5. CML output format requires ac-coupling of the differential outputs to a differential 100
 load at the receiver.
6. Includes effect of internal series 22
 resistor.
Table 3. Performance Characteristics (Continued)
(VDD = 1.8 V –5% to +10%, 2.5 V ±10%, or 3.3 V ±10%, TA = –40 to 85 °C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Notes:
1. Outputs at integer-related frequencies and using the same driver format.
2. Keep MultiSynth output frequency between 5 MHz to Fvco/8.
3. Only MultiSynth0 can have frequency inc/dec but MultiSynth0 can be routed to any output.
4. Spread spectrum is only available on clock outputs that are at 100 MHz and have the Rn divider set to 1.


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