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Moteur de recherche de fiches techniques de composants électroniques |
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Moteur de recherche de fiches techniques de composants électroniques |
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SI3454 Fiches technique(PDF) 11 Page - Silicon Laboratories |
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SI3454 Fiches technique(HTML) 11 Page - Silicon Laboratories |
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11 / 57 page  Si3454 Rev. 1.1 11 Table 5. I2C Bus Timing Specifications1,2,3,4,5,6 Parameter Symbol Test Condition Min Typ Max Unit Serial Bus Clock Frequency fSCL See Figure 5 0 — 800 kHz SCL High Time tSKH See Figure 5 300 — — ns SCL Low Time tSKL See Figure 5 650 — — ns Bus Free Time tBUF Between STOP and START con- ditions. See Figure 5 650 — — ns Start Hold Time tSTH Between START and first low SCL. See Figure 5 300 — — ns Start Setup Time tSTS Between SCL high and START condition. See Figure 5 300 — — ns Stop Setup Time tSPS Between SCL high and STOP condition. See Figure 5 300 — — ns Data Hold Time tDH See Figure 57 75 — — ns Data Setup Time tDS See Figure 5 100 — — ns Time from Hardware or Soft- ware Reset until Start of I2C Traffic tRESET Reset to start condition 5 — — ms Notes: 1. All specification voltages are referenced with respect to AGND and DGND at ground. Currents are defined as positive flowing into a pin and negative flowing out of a pin. 2. Not production tested (guaranteed by design). 3. All timing references measured at VIL and VIH. 4. SDAI must be low within ½ SCL clock cycle of SDAO going low for the following reasons: a.) During a read transaction, if the Si3454 is letting SDAO go high and another device is driving SDAO low, this should be recognized as bus contention, and the Si3454 should release the bus. If SDAO low is not present on SDAI within ½ clock cycle, the Si3454 will not recognize this as bus contention and will not release the bus. b.) During any I2C transaction, the Si3454 will ACK (SDAO low) when its address is sent. The Si3454 “expects” that SDAI will follow within ½ of the SCL clock cycle. If SDAI is not low, the Si3454 will release the bus. 5. SCL and SDA rise and fall times depend on bus pullup resistance and bus capacitance. 6. The time from a fault event to the INT pin being driven is software-defined. The Si3454 produces a new measurement result for the Port voltage or current every 3 msec and every 6 msec for the power supplies and temperature. After each port is monitored, the port status, port event registers, INT register, and INT pin are updated in sequence. For this reason, the INT pin can lag the contents of the event registers by approximately 5 ms. 7. 250 ns minimum and 350 ns maximum for the case where the Si3454 is transmitting data. |
Numéro de pièce similaire - SI3454 |
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Description similaire - SI3454 |
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