SI515 datasheet(9/22 Pages) SILABS

No de pièce	SI515

Description	VOLTAGE-CONTROLLED CRYSTAL OSCILLATOR

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Si515

Rev. 1.0

9

Table 7. Output Clock Jitter and Phase Noise (HCSL)

VDD = 1.8 V ±5%, 2.5 or 3.3 V ±10%, TA = –40 to +85 oC; Output Format = HCSL

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

Period Jitter

(RMS)

JPRMS

10k samples*

——

1.2

ps

Period Jitter

(Pk-Pk)

JPPKPK

10k samples*

——

11

ps

Phase Jitter

(RMS)

φJ

1.875 MHz to 20 MHz integration

bandwidth*(brickwall)

—0.25

0.30

ps

12 kHz to 20 MHz integration band-

width* (brickwall)

—0.8

1.0

ps

Phase Noise,

156.25 MHz

φN100 Hz

—

–75

—

dBc/Hz

1kHz

—

–98

—

dBc/Hz

10 kHz

—

–117

—

dBc/Hz

100 kHz

—

–127

—

dBc/Hz

1 MHz

—

–136

—

dBc/Hz

Spurious

SPR

LVPECL output, 156.25 MHz,

offset>10 kHz

—–75

—

dBc

*Note:

Applies to an output frequency of 100 MHz.

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