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TPS28225 Fiches technique(PDF) 11 Page - Texas Instruments

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No de pièce TPS28225
Description  TPS28225 High-Frequency 4-A Sink Synchronous MOSFET Drivers
Download  38 Pages
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Fabricant  TI1 [Texas Instruments]
Site Internet  http://www.ti.com
Logo TI1 - Texas Instruments

TPS28225 Fiches technique(HTML) 11 Page - Texas Instruments

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TPS28225
www.ti.com
SLUS710D – MAY 2006 – REVISED SEPTEMBER 2015
7.3 Feature Description
7.3.1 Undervoltage Lockout (UVLO)
The TPS28225 incorporates an under voltage lockout circuit that keeps the driver disabled and external power
FETs in an OFF state when the input supply voltage VDD is insufficient to drive external power FETs
reliably.During power up, both gate drive outputs remain low until voltage VDD reaches UVLO threshold, typically
3.5 V . Once the UVLO threshold is reached, the condition of the gate drive outputs is defined by the input PWM
and EN/PG signals. During power down the UVLO threshold is set lower, typically 3.0 V. The 0.5 V for the
TPS28225 hysteresis is selected to prevent the driver from turning ON and OFF while the input voltage crosses
UVLO thresholds, especially with low slew rate. The TPS28225 has the ability to send a signal back to the
system controller that the input supply voltage VDD is insufficient by internally pulling down the EN/PG pin. The
TPS28225 releases EN/PG pin immediately after the VDD has risen above the UVLO threshold.
7.3.2 Output Active Low
The output active-low circuit effectively keeps the gate outputs low even if the driver is not powered up. This
prevents open-gate conditions on the external power FETs and accidental turn on when the main power-stage
supply voltage is applied before the driver is powered up. For the simplicity, the output active low circuit is shown
in a block diagram as the resistor connected between LGATE and GND pins with another one connected
between UGATE and PHASE pins.
Copyright © 2006–2015, Texas Instruments Incorporated
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