Moteur de recherche de fiches techniques de composants électroniques |
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TMP112 Fiches technique(PDF) 6 Page - Texas Instruments |
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TMP112 Fiches technique(HTML) 6 Page - Texas Instruments |
6 / 35 page TMP112 SBOS473E – MARCH 2009 – REVISED DECEMBER 2015 www.ti.com 6.6 Timing Requirements See the Two-Wire Timing Diagrams section for timing diagrams. HIGH-SPEED FAST MODE MODE UNIT MIN MAX MIN MAX ƒ(SCL) SCL operating frequency V+ 0.001 0.4 0.001 2.85 MHz Bus-free time between STOP and START t(BUF) 600 160 ns condition Hold time after repeated START condition. t(HDSTA) 600 160 ns After this period, the first clock is generated. See Figure 10 t(SUSTA) repeated start condition setup time 600 160 ns t(SUSTO) STOP Condition Setup Time 600 160 ns t(HDDAT) Data hold time 100 900 25 105 ns t(SUDAT) Data setup time 100 25 ns t(LOW) SCL-clock low period V+ , see Figure 10 1300 210 ns t(HIGH) SCL-clock high period See Figure 10 600 60 ns tFD Data fall time See Figure 10 300 80 ns See Figure 10 300 ns tRD Data rise time SCLK ≤ 100 kHz, see Figure 10 1000 ns tFC Clock fall time See Figure 10 300 40 ns tRC Clock rise time See Figure 10 300 40 ns 6 Submit Documentation Feedback Copyright © 2009–2015, Texas Instruments Incorporated Product Folder Links: TMP112 |
Numéro de pièce similaire - TMP112_15 |
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Description similaire - TMP112_15 |
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