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TPS566250DDAR Fiches technique(PDF) 6 Page - Texas Instruments |
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TPS566250DDAR Fiches technique(HTML) 6 Page - Texas Instruments |
6 / 32 page VIL VIH TPS566250 SLVSCV3B – MARCH 2015 – REVISED JUNE 2015 www.ti.com 7.6 Timing Requirements MIN TYP MAX UNIT ON-TIME TIMER CONTROL ton SW On time VIN = 12 V, VOUT = 1.1 V 165 ns toff SW Minimum off time TA = 25 °C, FB = 0.5 V 275 325 ns SOFT START tSS Soft start time Internal soft start time 0.7 1 1.3 ms OUTPUT UNDERVOLTAGE PROTECTION t(UVPDEL) Hiccup delay time (power into short) 1.3 ms t(UVPEN) Hiccup off time before restart 10 ms SERIAL INTERFACE(1) (2) (3) Pulse width of spikes suppressed by input t(SP) 32 ns filter t(HD;STA) Hold time (repeated) START condition. 0.6 µs tLOW LOW period of SCL clock 1.3 µs tHIGH HIGH period of SCL clock 0.6 µs t(SU;STA) Set-up time for a repeated START condition 0.6 µs t(HD;DAT) Data Hold time 50 900 ns t(SU;DAT) Data set-up time 100 ns tr Rise time (SDA or SCL) 20+0.1Cb(3) 300 ns tf Fall time (SDA or SCL) 20+0.1Cb(3) 300 ns t(SU;STO) Set-up time for STOP condition 0.6 µs Bus free time between STOP and START t(BUF) 1.3 µs condition (1) Specified by design. Not production tested. (2) Refer to Figure 1 below for I2C Timing Definitions (3) Cb = capacitance of bus line in pF Figure 1. I2C Timing Definitions (reproduced from Phillips I2C spec Version 1.1) 6 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: TPS566250 |
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