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MC100EP196AMNG Fiches technique(PDF) 11 Page - ON Semiconductor |
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MC100EP196AMNG Fiches technique(HTML) 11 Page - ON Semiconductor |
11 / 18 page MC100EP196A http://onsemi.com 11 Figure 4. AC Reference Measurement IN IN Q Q tPHL tPLH VINPP = VIH(D) − VIL(D) VOUTPP = VOH(Q) − VOL(Q) Using the FTUNE Analog Input The analog FTUNE pin on the EP196 device is intended to add more delay in a tunable gate to enhance the 10 ps resolution capabilities of the fully digital EP196. The level of resolution obtained is dependent on the voltage applied to the FTUNE pin. To provide this further level of resolution, the FTUNE pin must be capable of adjusting the additional delay finer than the 10 ps digital resolution (See Logic Diagram). This requirement is easily achieved because a 60 ps additional delay can be obtained over the entire FTUNE voltage range (See Figure 5). This extra analog range ensures that the FTUNE pin will be capable even under worst case conditions of covering a digital resolution. Typically, the analog input will be driven by an external DAC to provide a digital control with very fine analog output steps. The final resolution of the device will be dependent on the width of the DAC chosen. To determine the voltage range necessary for the FTUNE input, Figure 5 should be used. There are numerous voltage ranges which can be used to cover a given delay range; users are given the flexibility to determine which one best fits their designs. Figure 5. Typical EP196A Delay versus FTUNE Voltage FTUNE VOLTAGE (V) −3.3 −2.97 −2.64 −2.31 −1.98 −1.65 −1.32 −0.99 −0.66 −0.33 0 90 80 70 60 50 40 30 20 10 0 −10 −40 °C 85 °C 25 °C VCC = 0 V VEE = −3.3 V VCC VEE Cascading Multiple EP196As To increase the programmable range of the EP196A, internal cascade circuitry has been included. This circuitry allows for the cascading of multiple EP196As without the need for any external gating. Furthermore, this capability requires only one more address line per added E196A. Obviously, cascading multiple programmable delay chips will result in a larger programmable range: however, this increase is at the expense of a longer minimum delay. Figure 6 illustrates the interconnect scheme for cascading two EP196As. As can be seen, this scheme can easily be expanded for larger EP196A chains. The D10 input of the EP196A is the CASCADE control pin. With the interconnect scheme of Figure 6 when D10 is asserted, it signals the need for a larger programmable range than is achievable with a single device and switches output pin CASCADE HIGH and pin CASCADE LOW. The A11 address can be added to generate a cascade output for the next EP196A. For a 2−device configuration, A11 is not required. |
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