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TPS70145 Fiches technique(PDF) 8 Page - Texas Instruments |
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TPS70145 Fiches technique(HTML) 8 Page - Texas Instruments |
8 / 42 page UVLO Comp + - + - + - + - Thermal Shutdown 2.5V + - Current Sense Reference Vref Vref ENA_1 ENA_1 120ms Delay 0.95xVref FB1 0.95xVref FB2 RisingEdge Deglitch Current Sense + - ENA_2 ENA_2 Vref VIN1 (2Pins) GND EN VIN2 (2Pins) SEQ (seeNoteB) FB1 (seeNoteA) PG1 MR2 RESET FB2 (seeNoteA) VIN1 MR1 VIN1 PG Comp RisingEdge Deglitch Reset Comp VOUT1 (2Pins) VOUT2 (2Pins) + - FallingEdge Deglitch 0.83 x Vref FB2 V UVComp OUT2 FallingEdge Deglitch 0.83 x Vref FB1 V UVComp OUT1 Power Sequence Logic ENA_1 ENA_2 VIN1 TPS70145, TPS70148 TPS70151, TPS70158 TPS70102 SLVS222I – DECEMBER 1999 – REVISED AUGUST 2010 www.ti.com Adjustable Voltage Version A. For most applications, FB1 and FB2 should be externally connected to resistor dividers as close as possible to the device. For other implementations, refer to FB terminals connection discussion in the Application Information section. B. If the SEQ terminal is floating at the input, VOUT2 powers up first 8 Submit Documentation Feedback Copyright © 1999–2010, Texas Instruments Incorporated |
Numéro de pièce similaire - TPS70145_15 |
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Description similaire - TPS70145_15 |
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