TPS65286 datasheet(6/46 Pages) TI

No de pièce	TPS65286

Description	TPS65286 Dual Power Distribution Switches With 4.5-V to 28-V Input Voltage, 6-A Output Current Synchronous Buck Regulator

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TPS65286

SLVSCG1 – MARCH 2014

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7.4 Thermal Information

TPS65286

THERMAL METRIC(1)

RHD

UNIT

28 TERMINAL

RθJA

Junction-to-ambient thermal resistance(2)

35.6

RθJCtop

Junction-to-case (top) thermal resistance(3)

24.2

RθJB

Junction-to-board thermal resistance(4)

7.9

°C/W

RψJT

Junction-to-top characterization parameter(5)

0.3

RψJB

Junction-to-board characterization parameter(6)

7.96

RθJCbot

Junction-to-case (bottom) thermal resistance(7)

1.1

(1)

For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

(2)

The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as

specified in JESD51-7, in an environment described in JESD51-2a.

(3)

The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-

standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.

(4)

The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB

temperature, as described in JESD51-8.

(5)

The junction-to-top characterization parameter,

ψJT, estimates the junction temperature of a device in a real system and is extracted

from the simulation data for obtaining

θJA, using a procedure described in JESD51-2a (sections 6 and 7).

(6)

The junction-to-board characterization parameter,

ψJB, estimates the junction temperature of a device in a real system and is extracted

from the simulation data for obtaining

θJA , using a procedure described in JESD51-2a (sections 6 and 7).

(7)

The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific

JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.

Spacer

7.5 Electrical Characteristics

TJ = 25°C, VIN = 24 V, fSW = 500 kHz, RnFAULTx = 100 kΩ (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

INPUT SUPPLY

VIN

Input voltage range

VIN1 and VIN2

4.5

28

V

IDDSDN

Shutdown supply current

EN1 = EN2 = low

7.60

15

µA

Quiescent current without buck

EN = high, ENx = low, FB = 1 V

IDDQ_NSW

0.8

mA

switching

Without buck switching

Input quiescent current with buck

EN = high, ENx = low, FB = 0.6 V

IDDQ_SW

26

mA

switching

With buck switching

Rising VIN

4

4.25

4.50

UVLO

VIN under voltage lockout

Falling VIN

3.75

4

4.25

V

Hysteresis

0.25

Low side gate driver, controller,

V7V load current = 0 A,

V7V

6.10

6.25

6.4

V

biasing supply

VIN = 24 V

IOCP_V7V

Current limit of V7V LDO

83

mA

ENABLE

VENR

Enable threshold

Rising

1.21

1.26

V

VENF

Enable threshold

Falling

1.10

1.17

V

IENL

Enable pull-up current

EN = 1 V

3

µA

IENH

Enable pull-up current

EN = 1.5 V

6

µA

IENHYS

Enable hysteresis current

3

µA

6

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