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Moteur de recherche de fiches techniques de composants électroniques |
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Moteur de recherche de fiches techniques de composants électroniques |
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TPS54341DPRT Fiches technique(PDF) 2 Page - Texas Instruments |
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TPS54341DPRT Fiches technique(HTML) 2 Page - Texas Instruments |
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2 / 48 page  BOOT VIN EN SS/TR RT/CLK PWRGD SW GND COMP FB 10 9 1 2 3 4 5 8 7 6 TPS54341 SLVSC61 – NOVEMBER 2013 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. DEVICE INFORMATION PIN CONFIGURATION DPR PACKAGE (TOP VIEW) PIN FUNCTIONS PIN I/O DESCRIPTION NAME NO. A bootstrap capacitor is required between BOOT and SW. If the voltage on this capacitor is below the BOOT 1 O minimum required to operate the high-side MOSFET, the gate drive switches off until the capacitor refreshes. Error amplifier output and input to the output switch current (PWM) comparator. Connect frequency COMP 7 O compensation components to this pin. Enable pin, with internal pullup current source. Pull below 1.2 V to disable. Float to enable. Adjust the input EN 3 I undervoltage lockout with two resistors. See the Enable and Adjusting Undervoltage Lockout section. FB 6 I Inverting input of the transconductance (gm) error amplifier. GND 8 – Ground Power Good is an open drain output that asserts low if the output voltage is out of regulation due to thermal PWRGD 10 O shutdown, dropout, over-voltage or EN shut down Resistor Timing and External Clock. An internal amplifier holds this pin at a fixed voltage when using an external resistor to ground to set the switching frequency. If the pin is pulled above the PLL upper threshold, RT/CLK 5 I a mode change occurs and the pin becomes a synchronization input. The internal amplifier is disabled and the pin is a high-impedance clock input to the internal PLL. If clocking edges stop, the internal amplifier re- enables and the operating mode returns to resistor frequency programming. Soft-start and Tracking. An external capacitor connected to this pin sets the output rise time. Because the SS/TR 4 I voltage on this pin overrides the internal reference, SS/TR can be used for tracking and sequencing. SW 9 I The source of the internal high-side power MOSFET and switching node of the converter. VIN 2 I Input supply voltage with 4.5-V to 42-V operating range. The GND pin must be electrically connected to the exposed pad on the printed circuit board for proper Thermal Pad 11 – operation. 2 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: TPS54341 |
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