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TPS54313 Fiches technique(PDF) 11 Page - Texas Instruments

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No de pièce TPS54313
Description  TPS5431x 3-V to 6-V Input, 3-A Output Synchronous Buck PWM Switcher With Integrated FETs (SWIFT??
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Fabricant  TI [Texas Instruments]
Site Internet  http://www.ti.com
Logo TI - Texas Instruments

TPS54313 Fiches technique(HTML) 11 Page - Texas Instruments

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background image
100 k
Switching Frequency
500 [kHz]
R
W
=
´
TPS54311, TPS54312, TPS54313
TPS54314, TPS54315, TPS54316
www.ti.com
SLVS416C – FEBRUARY 2002 – REVISED JANUARY 2015
7.3.5 Oscillator and PWM Ramp
The oscillator frequency can be set to internally fixed values of 350 kHz or 550 kHz using the FSEL pin as a
static digital input. If a different frequency of operation is required for the application, the oscillator frequency can
be externally adjusted from 280 kHz to 700 kHz by connecting a resistor to the RT pin to ground and floating the
FSEL pin. The switching frequency is approximated by the following equation, where R is the resistance from RT
to AGND:
(3)
Table 2. Summary of the Frequency Selection Configurations
SWITCHING FREQUENCY
FSEL PIN
RT PIN
350 kHz, internally set
Float or AGND
Float
550 kHz, internally set
≥2.5 V
Float
Externally set 280 kHz to 700 kHz
Float
R = 68 k
Ω to 180 kΩ
7.3.6 Error Amplifier
The high performance, wide bandwidth, voltage error amplifier is gain limited to provide internal compensation of
the control loop. The user is given limited flexibility in choosing output L and C filter components. Inductance
values of 4.7 µH to 10 µH are typical and available from several vendors. The resulting designs exhibit good
noise and ripple characteristics, along with exceptional transient response. Transient recovery times are typically
in the range of 10 to 20 µs.
7.3.7 PWM Control
Signals from the error amplifier output, oscillator, and current limit circuit are processed by the PWM control logic.
Referring to the internal block diagram, the control logic includes the PWM comparator, OR gate, PWM latch,
and portions of the adaptive dead-time and control logic block. During steady-state operation below the current
limit threshold, the PWM comparator output and oscillator pulse train alternately reset and set the PWM latch.
Once the PWM latch is set, the low-side FET remains on for a minimum duration set by the oscillator pulse
duration. During this period, the PWM ramp discharges rapidly to its valley voltage. When the ramp begins to
charge back up, the low-side FET turns off and high-side FET turns on. As the PWM ramp voltage exceeds the
error amplifier output voltage, the PWM comparator resets the latch, thus turning off the high-side FET and
turning on the low-side FET. The low-side FET remains on until the next oscillator pulse discharges the PWM
ramp
During transient conditions, the error amplifier output could be below the PWM ramp valley voltage or above the
PWM peak voltage. If the error amplifier is high, the PWM latch is never reset and the high-side FET remains on
until the oscillator pulse signals the control logic to turn the high-side FET off and the low-side FET on. The
device operates at its maximum duty cycle until the output voltage rises to the regulation set-point, setting
VSENSE to approximately the same voltage as Vref. If the error amplifier output is low, the PWM latch is
continually reset and the high-side FET does not turn on. The low-side FET remains on until the VSENSE
voltage decreases to a range that allows the PWM comparator to change states. The TPS5431x is capable of
sinking current continuously until the output reaches the regulation set-point.
If the current limit comparator trips for longer than 100 ns, the PWM latch resets before the PWM ramp exceeds
the error amplifier output. The high-side FET turns off and low-side FET turns on to decrease the energy in the
output inductor and consequently the output current. This process is repeated each cycle in which the current
limit comparator is tripped.
7.3.8 Dead-Time Control and MOSFET Drivers
Adaptive dead-time control prevents shoot-through current from flowing in both N-channel power MOSFETs
during the switching transitions by actively controlling the turnon times of the MOSFET drivers. The high-side
driver does not turn on until the voltage at the gate of the low-side FET is below 2 V. The high-side and low-side
drivers are designed with 300 mA source and sink capability to quickly drive the power MOSFETs gates. The
low-side driver is supplied from VIN, while the high-side drive is supplied from the BOOT pin. A bootstrap circuit
uses an external BOOT capacitor and internal 2.5-
Ω bootstrap switch connected between the VIN and BOOT
pins. The integrated bootstrap switch improves drive efficiency and reduces external component count.
Copyright © 2002–2015, Texas Instruments Incorporated
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Product Folder Links: TPS54311 TPS54312 TPS54313 TPS54314 TPS54315 TPS54316


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