TPS7B4250-Q1

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SLVSCA0B – OCTOBER 2013 – REVISED JULY 2015

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)

(1)

MIN

MAX

UNIT

(2) (3)

–20

45

V

–1

22

V

–0.3

22

V

7

V

–40

150

°C

–65

150

°C

(1)

Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings

only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating

conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2)

All voltage values are with respect to ground, GND.

(3)

Absolute maximum voltage.

6.2 ESD Ratings

VALUE

UNIT

±4000

Electrostatic discharge

V

Charged-device model (CDM), per AEC Q100-011

±1000

(1)

AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

(1)

MIN

MAX

UNIT

Unregulated input

4

40

V

regulated output

1.5

18

V

ADJ/EN

Adjust input and enable input voltage

1.5

18

V

ADJ voltage minus input voltage

5

V

1

50

µF

Output ESR requirements

0.001

20

Ω

Operating junction temperature

–40

150

°C

(1)

Within the functional range, the IC operates as described in the circuit description. The electrical characteristics are specified within the

conditions given in the related electrical characteristics table.

(2)

The minimum output capacitance requirement is applicable for a worst-case capacitance tolerance of 30%.

6.4 Thermal Information

TPS7B4250-Q1

DBV (SOT-23)

UNIT

5 PINS

Junction-to-ambient thermal resistance

171.7

°C/W

Junction-to-case (top) thermal resistance

81.1

°C/W

Junction-to-board thermal resistance

31.7

°C/W

Junction-to-top characterization parameter

4.5

°C/W

Junction-to-board characterization parameter

31.2

°C/W

Junction-to-case (bottom) thermal resistance

N/A

°C/W

(1)

For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report, SPRA953.

(2)

The thermal data is based on the JEDEC standard high K profile, JESD 51-7. Two-signal, two-plane, four-layer board with 2-oz. copper.

The copper pad is soldered to the thermal land pattern. Also, correct attachment procedure must be incorporated.

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