Moteur de recherche de fiches techniques de composants électroniques |
|
TC534CKW Fiches technique(PDF) 6 Page - Microchip Technology |
|
TC534CKW Fiches technique(HTML) 6 Page - Microchip Technology |
6 / 22 page TC530/TC534 DS21433B-page 6 © 2002 Microchip Technology Inc. 16 16 23 20 DOUT Logic Level Output. Serial port data output pin. This pin is enabled only when R/W is high. 17 17 24 21 DCLK Logic Input, Positive and Negative Edge Triggered. Serial port clock. When R/W is high, serial data is clocked out of the TC530/TC534A (on DOUT) at each high-to-low transition of DCLK. A/D initialization data (LOAD VALUE) is clocked into the TC530/TC534 (on DIN) at each low-to-high transi- tion of DCLK.A maximum serialport DCLK frequency of 3MHz is permitted. 18 18 25 22 DIN Logic Level Input. Serial port input pin. The A/D converter integration time (TINT) and Auto Zero time (TAZ) values are determined by the LOAD VALUE byte clocked into this pin. This initialization must take place at power up, and can be rewritten (or modified and rewritten) at any time. The LOAD VALUE is clocked into DIN MSB first. 19 19 26 23 R/W Logic Level Input. This pin must be brought low to perform a write to the serial port (e.g. initialize the A/D converter). The DOUT pin of the serial port is enabled only when this pin is high. 20 20 27 24 EOC Open Drain Output. End-of-Conversion (EOC)is asserted any time the TC530/TC534 is in the AZ phase of conver- sion. This occurs when either the TC530/TC534 initiates a normal AZ phase or when RESET is pulled high. EOC is returned high when the TC530/TC534 exits AZ. Since EOC is driven low immediately following completion of a conver- sion cycle, it can be used as a DATA READY processor interrupt. 21 21 30 28 RESET Logic Level Input. It is necessary to force the TC530/TC534 into the Auto Zero phase when power is initially applied. This is accomplished by momentarily taking RESET high. Using an I/O port line from the microprocessor or by apply- ing an external system reset signal or by connecting a 0.01 µF capacitor from the RESET input to VDD.Conver- sions are performed continuously as long as RESET is low and conversion is halted when RESET is high. RESET may therefore be used in a complex system to momentarily sus- pend conversion (for example, while the address lines of an input multiplexer are changing state). In this case, RESET should be pulled high only when the EOC is LOW to avoid excessively long integrator discharge times which could result in erroneous conversion. (See Applications Section). 22 22 32 30 VCCD Analog Input. Power supply connection for digital logic and serial port. Proper power-up sequencing is critical, see the Applications section. 23 23 34 32 OSC Input. The negative power supply converter normally runs at a frequency of 100kHz. This frequency can be slowed down to reduce quiescent current by connecting an external capacitor between this pin and V+DD. See Section 6.0, Typical Characteristics. 25 25 37 35 VDD Analog Input. Power supply connection for the A/D analog section and DC-DC converter. Proper power-up sequencing is critical, (See the Applications section). TABLE 2-1: PIN FUNCTION TABLE (CONTINUED) Pin Number (TC530) 28-Pin PDIP Pin Number (TC530) 28-Pin SOIC Pin Number (TC534) 40-Pin PDIP Pin Number (TC534) 44-Pin PQFP Symbol Description |
Numéro de pièce similaire - TC534CKW |
|
Description similaire - TC534CKW |
|
|
Lien URL |
Politique de confidentialité |
ALLDATASHEET.FR |
ALLDATASHEET vous a-t-il été utile ? [ DONATE ] |
À propos de Alldatasheet | Publicité | Contactez-nous | Politique de confidentialité | Echange de liens | Fabricants All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |